Abstract: A test device is provided for testing stability of a computer when the computer is started up or shut down. The test device includes a monolithic chip and a switch module. The monolithic chip includes an input port and an output port. The input port receives a high level or a low level signal from the computer. A test control module is disposed in the monolithic chip. The switch module includes an input pin coupled to the output port of the monolithic chip and a pair of output pins corresponding to the input pin. The pair of output pins is connected to the computer, for controlling the computer to be started up or shut down. The input port of the monolithic chip is connected to the computer for detecting a state of the computer.

Abstract: A method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract: A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

Abstract: A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for sending test signals to the input interface and receiving feedback signals from the output interface for facilitating locating and recording errors during testing of the computer. A testing method for testing the computer is also disclosed.

Abstract: A testing and alert device for power leakages of a computer includes a basic input/output system (BIOS) chip located on a motherboard of the computer, a south bridge chip connected to the BIOS chip, and an alarm device controlled by the BIOS chip. The south bridge chip has a first general purpose input/output terminal capable of being coupled to a ground of an exterior power source. The BIOS chip is capable of detecting the input signal of the first general purpose input/output terminal of the south bridge chip and outputting an alarm command to initiate the alarming device when the input signal from the first general purpose input/output terminal is at a high level.

Abstract: A method of manufacturing a multi-layer board is disclosed. The method may include forming a detachable separation layer over a support; forming a first solder resist layer over the separation layer; stacking a metal foil over the first solder resist layer; forming a circuit pattern over the metal foil; forming an insulation part over the first solder resist layer such that the circuit pattern is covered; forming a second solder resist layer over the insulation part; and separating a circuit stack unit, which includes the first solder resist layer, the metal foil, the circuit pattern, the insulation part, and the second solder resist layer, from the support by disconnecting the separation layer and the support. This method uses a simple process to reduce manufacture costs and shorten manufacture times.

Abstract: A calibration device for a nozzle suitable for calibrating a nozzle of a semiconductor apparatus is provided. The semiconductor apparatus includes a chuck with a center hole with radius R1. A cap with outer radius R3 is disposed outside the nozzle with outer radius R2. The calibration device includes a jig including an upper portion, a lower portion and a recess in the front surface of the upper portion. The recess includes an outer portion with depth D1 and radius R4 larger than R3 and an inner portion with depth D2 larger than D1 and radius R5 larger than R2. The lower portion with a radius R6 less than R1 is connected to the back surface of the upper portion for fixing the jig in the center hole. The values of (R4?R3), (R5?R2) and (R1?R6) are in the tolerable calibration inaccuracy range.

Abstract: A calibration device for a nozzle suitable for calibrating a nozzle of a semiconductor apparatus is provided. The semiconductor apparatus includes a chuck with a center hole with radius R1. A cap with outer radius R3 is disposed outside the nozzle with outer radius R2. The calibration device includes a jig including an upper portion, a lower portion and a recess in the front surface of the upper portion. The recess includes an outer portion with depth D1 and radius R4 larger than R3 and an inner portion with depth D2 larger than D1 and radius R5 larger than R2. The lower portion with a radius R6 less than R1 is connected to the back surface of the upper portion for fixing the jig in the center hole. The values of (R4?R3), (R5?R2) and (R1?R6) are in the tolerable calibration inaccuracy range.

Abstract: A package substrate and a method of manufacturing the package substrate are disclosed. The method of manufacturing the package substrate may include stacking a second metal layer in which at least one hole is formed over a first metal layer, stacking a barrier layer over the first metal layer exposed in the hole and over the second metal layer, forming at least one bump by filling the hole with a conductive metal, stacking an insulation layer over the bump and forming a circuit pattern over the insulation layer, and removing the first metal layer, the second metal layer, and the barrier layer.

Abstract: A method of manufacturing a printed circuit board having solder balls. The method may include: stacking a second carrier, in which at least one hole is formed, over one side of a first carrier; forming at least one solder bump by filling the hole with a conductive material; forming a circuit pattern layer, which is electrically connected with the solder bump, on the second carrier; and exposing the solder bump by removing the first carrier and the second carrier. Using this method, uniform hemispherical solder balls with fine pitch can be formed as a part of the manufacturing process, without having to attach the solder balls separately. Carriers may be used to serve as supports during the manufacturing process, whereby deformations can be prevented in the board.

Abstract: A substrate manufacturing method is disclosed. A substrate manufacturing method, comprising: providing a support body on which a first separation layer is formed; forming a second separation layer on the first separation layer; forming an adhesion layer which covers the first separation layer and the second separation layer; forming a circuit stack body on the adhesion layer; cutting the circuit stack body, the adhesion layer and the second separation layer to a pre-determined shape; and forming a circuit stack unit by separating the second layer from the first layer, provides easy separation of the circuit stack pattern, which formed on the support body, from the support body and reduced manufacturing cost by reducing number of process and required materials for manufacturing coreless thin substrate.

Abstract: A multilayered printed circuit board and a fabricating method thereof are disclosed. A method that includes repeating processes of forming at least one circuit pattern, and at least one insulation layer that covers the circuit pattern, over a carrier and interconnecting circuit patterns on different layers with vias; stacking a metal stiffener over the insulation layer; repeating processes of forming at least one insulation layer and at least one circuit pattern over the stiffener and interconnecting circuit patterns on different layers with vias; and removing the carrier, can be used to reduce warpage in the board and improve workability.

Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract: The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.

Abstract: A multilayered printed circuit board is disclosed. A method of manufacturing the multilayered printed circuit board, which includes: forming a metal layer and a lower-circuit-forming pattern in order on a carrier, and forming a lower circuit by filling a conductive material in the lower-circuit-forming pattern; removing the lower-circuit-forming pattern, stacking an insulation resin, and forming at least one via hole connecting with the lower circuit; forming at least one inner circuit and at least one interlayer connector connecting the inner circuit with the lower circuit on the insulation resin, to form a pair of circuit parts; and aligning the pair of circuit parts, attaching the pair of circuit parts to each other, and removing the carrier and the metal layer, allows the forming of fine-lined circuits and provides a thin board, while preventing bending and warpage in the board.

Abstract: A brushless DC motor prevents disconnection of a magnetic flux and to minimize leakage of the magnetic flux, thereby reducing torque ripple. A plurality of magnetic flux-disconnection preventing holes are arranged in an outer periphery of a rotor core between installing holes into which magnets are fitted. The plurality of magnetic flux-disconnection preventing holes are symmetrical at both sides about a first line connecting a center of the rotor core to a center between the adjacent installing holes, and an angle between the first line and a second line connecting the center of the rotor core to an outermost end of the plurality of magnetic flux-disconnection preventing holes is about 15˜20°. A length between an outer periphery of the rotor core and an outer periphery of the plurality of magnetic flux-disconnection preventing holes is smaller than a gap between the rotor core and the stator.

Abstract: A motherboard assembly of a computer includes a motherboard (80) and an expansion device. The expansion device is connected to the motherboard. The expansion device includes a BIOS chip (10), a first connector (20) and at least one second connector (30). The first connector is connected to a socket (40) mounted on the motherboard. The second connector is capable of connecting to a burning device (90) for restoring the BIOS chip. The BIOS chip is connected to the first connector, the second connector, and to a signal choice terminal of the motherboard which acts to access the BIOS chip through the first connector and the socket such that the BIOS chip of the expansion device can replace a BIOS chip mounted on the motherboard to be accessed when the computer is powered up to be tested, thereby protecting the BIOS chip mounted on the motherboard being damaged in test.

Abstract: A BIOS chip expansion card for starting a computer when the computer needs to be tested, includes a BIOS chip for starting the computer a first connector configured for connecting with a motherboard of the computer, and a switch member connected to the BIOS chip and the first connector for controlling communication therebetween, thereby controlling communication between the BIOS chip and the motherboard of the computer. Wherein when the BIOS chip communicates with the motherboard, the computer is started via the BIOS chip so that the computer can be tested.

Abstract: A semiconductor memory module having a reverse mounted chip resistor, and a method of fabricating the same are provided. By reverse mounting the chip resistor on the semiconductor memory module, the resistive material is protected, thereby preventing open circuits caused by damage to the resistive material. Also, a chip-resistor connection pad of a module substrate is formed to extend higher from the module substrate than other connection pads connected to other elements. Thus, the resistive material of the chip resistor does not contact the module substrate, thereby preventing poor alignment and defective connections.

Abstract: A test device is provided for testing stability of a computer when the computer is started up or shut down. The test device includes a monolithic chip and a switch module. The monolithic chip includes an input port and an output port. The input port receives a high level or a low level signal from the computer. A test control module is disposed in the monolithic chip. The switch module includes an input pin coupled to the output port of the monolithic chip and a pair of output pins corresponding to the input pin. The pair of output pins is connected to the computer, for controlling the computer to be started up or shut down. The input port of the monolithic chip is connected to the computer for detecting a state of the computer.