Abstract: A method of attaching a molecular layer to a substrate includes attaching a temporary protecting group(s) to a molecule having a molecular switching moiety with first and second connecting groups attached to opposed ends thereof. The temporary protecting group(s) is attached to the first and/or second connecting group so as to cause the opposed ends of the switching moiety to exhibit a difference in hydrophilicity such that one of the ends remains at at least one of a water/solvent interface and a water/air interface, and the other end remains in air during a Langmuir-Blodgett (LB) process. An LB film is formed on the interface. The temporary protecting group(s) is removed. The substrate is passed through the LB film to form the molecular layer chemically bonded on the substrate. The difference in hydrophilicity between the opposed ends causes formation of a substantially well-oriented, uniform LB film at the interface.

Abstract: Disclosed are photoluminescent tiles containing photoluminescent materials, and manufacturing methods thereof. A tile is filled or glazed with photoluminescent glaze powder including photoluminescent phosphor comprising a MAl2O4 compound (M: metal) as a matrix, and then baked, thereby obtaining the photoluminescent tiles. Since the photoluminescent tiles can be manufactured via a dry process, the manufacturing method is convenient and enables mass production via process automation. Additionally, the photoluminescent tiles of the present invention can be baked at a high temperature, and do not have degradations, such as fine cracks on the photoluminescent materials.

Abstract: The present invention relates to a protease, and more specifically to a protease derived from Aranicola proteolyticus, a gene coding for said enzyme, a gene expression system for said protease, a process for purifying the protease, and the uses of said protease in industrial applications, such as for example, detergents, cosmetics, leather processing agents, chemicals for laboratory research, solubilizing or softening agents for food, meat modifier, feed or food additives, or oil and fat separating agents, as well as pharmaceutical compositions.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: The present invention relates to the fast code acquisition methods based on signed-rank statistic. In more detail, it presents novel detectors required for PN (PN) code acquisition in DS/SS system. In accordance with the present invention, first, the LOR (LOR) detector is derived and then the LSR (LSR) and MSR (MSR) detectors using approximate score functions are proposed. It is compared the single-dwell scheme without the verification mode using the proposed LSR and MSR detectors with that using the conventional squared-sum (SS) and modified sign (MS) detectors.

Abstract: The present disclosure provides a system and method for an SS7 gateway for wireless networks.

Abstract: Provided is an optical module including a microstrip line, a traveling wave type optical device positioned in the end of the microstrip line, and at least one balanced open stub connected to the microstrip line for the impedance matching at a specific frequency such as 40 GHz and 60 GHz. For the fine tuning, laser trimming can be applied to the stub. A transition region is formed between the optical device and the microstrip line. A termination resistor is formed to face the microstrip line with the optical device therebetween. A bandwidth can be controlled at a specific frequency by adjusting a number of the stubs or a value of the termination resistor.

Abstract: The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

Abstract: A 2×2 opto-mechanical switch is disclosed. A first embodiment of the present invention utilizes a transmitting compact parallel prism and four or two pieces of the 45-degree prism to increase the beam separation. The compact parallel prism keeps a much smaller load to the relay arm. This makes the current invention less sensitive to the ambient shock and vibration. A second embodiment of the present invention utilizes a similar transmitting compact parallel prism and two wedge prisms which has similar advantages. The compact prism applies a small loading force to the relay arm. Both of these embodiments also feature superior thermal and mechanical stability. An opto-mechanical switch in accordance with the present invention utilizes a transmitting design and thus is more stable to ambient thermal or mechanical change. The embodiments of the present invention also feature much better repeatability than the conventional 2×2 optical switches.

Abstract: The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit portion and active channel regions of pixel portion. This may be achieved by having a different number of grain boundaries included in the polycrystalline silicon thin film formed in active channel regions of a switching thin film transistor and a driving thin film transistor formed in the pixel portion, and by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a thin film transistor for driving the pixel portion for each red, green and blue of the pixel portion.

Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

Abstract: A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g

Abstract: A control circuit for command signals of a clock generator includes a power supply end, an output end, a control end, a diode, a first resistor and a second resistor. The first resistor, the diode, and the second resistor are connected in series between the power supply end and the ground. The diode has an anode connected to the first resistor and a cathode connected to the second resistor. The control end is connected to a node between the diode and the second resistor; the output end is connected to a node between the diode and the first resistor. The output end outputs the command signals to the clock generator.

Abstract: The disclosure is a device for applying a test voltage from the external of a memory device in a burn-in test mode. An internal voltage generator for a burn-in test is comprised of pad means receiving an external voltage, switching means turned on in the burn-in test mode, and an internal voltage generating means. An external voltage applied to the pad means during the burn-in test mode is transferred to the internal voltage generating means by way of the switching means.

Abstract: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a portion of the active pattern where the first insulation film is formed; a second insulation film on the substrate; forming a plurality of first contact holes exposing a portion of the source and drain regions and a second contact hole exposing a portion of the data line; forming a source electrode from a transparent conductive material connected to a source region within the respective first contact hole and a data line within the second contact hole; and forming a pixel and a drain electrodes from the transparent conductive material connected to a drain region within the respective first contact hole.

Abstract: A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.