Patents by Inventor Yong CHA

Yong CHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 10147731
    Abstract: A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jae Yong Cha
  • CATALYST FOR OXIDATIVE DEHYDROGENATION AND METHOD OF PREPARING THE SAME
    Publication number: 20180333702
    Abstract: The present invention relates to a catalyst for oxidative dehydrogenation and a method of preparing the same. More particularly, the present invention provides a catalyst for oxidative dehydrogenation having a porous structure which may easily control heat generation due to high-temperature and high-pressure reaction conditions and side reaction due to the porous structure and thus exhibits superior product selectivity, and a method of preparing the catalyst.
    Type: Application
    Filed: November 30, 2016
    Publication date: November 22, 2018
    Applicant: LG CHEM, LTD.
    Inventors: Myung Ji SUH, Yoon Jae MIN, Dong Hyun KO, Kyong Yong CHA, Se Won BAEK, Jun Kyu HAN
  • CATALYST FOR OXIDATIVE DEHYDROGENATION AND METHOD OF PREPARING THE SAME
    Publication number: 20180290126
    Abstract: Disclosed are a catalyst for oxidative dehydrogenation and a method of preparing the same. More particularly, a catalyst for oxidative dehydrogenation of butene having a high butene conversion rate and superior side reaction inhibition effect and thus having high reactivity and high selectivity for a product by preparing metal oxide nanoparticles and then fixing the prepared metal oxide nanoparticles to a support, and a method of preparing the same are provided.
    Type: Application
    Filed: May 18, 2017
    Publication date: October 11, 2018
    Inventors: Seongmin KIM, Dong Hyun KO, Kyong Yong CHA, Dae Heung CHOI, Myung Ji SUH, Jun Kyu HAN, Sun Hwan HWANG, Jun Han KANG, Joo Hyuck LEE, Hyun Seok NAM, Ye Seul HWANG, Sang Jin HAN
  • METHOD OF PREPARING ZINC FERRITE CATALYST
    Publication number: 20180229221
    Abstract: The present disclosure relates to a method of preparing a zinc ferrite catalyst. More particularly, the present invention relates to a method of preparing a zinc ferrite catalyst comprising a) a step of dissolving a zinc precursor and an iron (III) precursor in water to prepare an aqueous metal precursor solution; b) a step of precipitating a solid catalyst precursor while vaporizing water in the aqueous metal precursor solution; and c) a step of firing the precipitated solid catalyst precursor to prepare a zinc ferrite catalyst. In accordance with the present disclosure, the method of preparing a zinc ferrite catalyst can be simply carried out without a pH adjustment step and can secure reproducibility.
    Type: Application
    Filed: March 16, 2017
    Publication date: August 16, 2018
    Inventors: Ye Seul HWANG, Dong Hyun KO, Kyong Yong CHA, Dae Heung CHOI
  • FERRITE-BASED CATALYST COMPOSITE, METHOD OF PREPARING THE SAME, AND METHOD OF PREPARING BUTADIENE USING THE SAME
    Publication number: 20180214854
    Abstract: The present invention relates to a ferrite-based catalyst composite, a method of preparing the same, and a method of preparing butadiene using the same. More particularly, the present invention provides a ferrite-based catalyst composite having a shape that allows effective dispersion of excess heat generated in a butadiene production process and prevention of catalyst damage and side reaction occurrence by reducing direct exposure of a catalyst to heat, a method of preparing the ferrite-based catalyst composite, and a method of preparing butadiene capable of lowering the temperature of a hot spot and reducing generation of Cox by allowing active sites of a catalyst to have a broad temperature gradient (profile) during oxidative dehydrogenation using the ferrite-based catalyst composite, and thus, providing improved process efficiency.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 2, 2018
    Inventors: Dae Heung CHOI, Dong Hyun KO, Kyong Yong CHA, Myung Ji SUH, Ye Seul HWANG, Sun Hwan HWANG, Seong Min KIM, Jun Han KANG, Joo Hyuck LEE, Hyun Seok NAM, Sang Jin HAN, Jun Kyu HAN
  • Semiconductor packages
    Patent number: 10037938
    Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keung Beum Kim, Hyunjong Moon, Seung-Yong Cha
  • METHOD OF PREPARING CATALYST FOR OXIDATIVE DEHYDROGENATION
    Publication number: 20180207621
    Abstract: The present invention relates to a method of preparing a catalyst for oxidative dehydrogenation. More particularly, the present invention provides a method of preparing a catalyst for oxidative dehydrogenation providing superior selectivity and yield for a conjugated diene according to oxidative dehydrogenation by constantly maintaining pH of a coprecipitation solution using a drip-type double precipitation method to adjust an ?-iron oxide content in a catalyst in a predetermined range.
    Type: Application
    Filed: March 15, 2017
    Publication date: July 26, 2018
    Inventors: Jun Kyu HAN, Dong Hyun KO, Kyong Yong CHA, Myung Ji SUH, Sun Hwan HWANG, Seong Min KIM
  • CATALYST FOR COATING SURFACE OF POROUS MATERIAL AND METHOD OF TREATING SURFACE OF POROUS MATERIAL
    Publication number: 20180186711
    Abstract: The present invention relates to a catalyst for coating a surface of a porous material and a method of treating the surface of the porous material. More particularly, when the catalyst for coating a surface of a porous material and the method of treating the surface of the porous material of the present invention are used for butadiene synthesis reaction under high gas space velocity and high pressure conditions, heat generation may be easily controlled and differential pressure may be effectively alleviated, thereby providing improved reactant conversion rate and product selectivity.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 5, 2018
    Inventors: Myung Ji SUH, Jun Han KANG, Dong Hyun KO, Seong Min KIM, Hyun Seok NAM, Joo Hyuck LEE, Kyong Yong CHA, Dae Heung CHOI, Sang Jin HAN, Jun Kyu HAN, Sun Hwan HWANG, Ye Seul HWANG
  • ELECTRONIC DEVICE PACKAGE
    Publication number: 20180190635
    Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.
    Type: Application
    Filed: September 6, 2017
    Publication date: July 5, 2018
    Inventors: JU-YOUN CHOI, EUN-SEOK SONG, SEUNG-YONG CHA, YUN-HEE LEE
  • CATALYST FOR OXIDATIVE DEHYDROGENATION AND METHOD OF PREPARING THE SAME
    Publication number: 20180133698
    Abstract: The present invention relates to a method of preparing a catalyst for oxidative dehydrogenation. More particularly, the method of preparing a catalyst for oxidative dehydrogenation includes a first step of preparing an aqueous iron-metal precursor solution by dissolving a trivalent cation iron (Fe) precursor and a divalent cation metal (A) precursor in distilled water; a second step of obtaining a slurry of an iron-metal oxide by reacting the aqueous iron-metal precursor solution with ammonia water in a coprecipitation bath to form an iron-metal oxide (step b) and then filtering the iron-metal oxide; and a third step of heating the iron-metal oxide slurry. In accordance with the present invention, a metal oxide catalyst, as a catalyst for oxidative dehydrogenation, having a high spinel phase structure proportion may be economically prepared by a simple process.
    Type: Application
    Filed: March 7, 2017
    Publication date: May 17, 2018
    Inventors: Kyong Yong CHA, Myung Ji SUH, Dong Hyun KO, Dae Heung CHOI, Ye Seul HWANG, Jun Kyu HAN, Sun Hwan HWANG, Seong Min KIM
  • IMAGE SENSOR PACKAGE
    Publication number: 20180138225
    Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 17, 2018
    Inventors: Yong-hoon KIM, Ji-chul KIM, Seung-yong CHA, Jae-choon KIM
  • Method of preparing conjugated diene and device therefor
    Patent number: 9969661
    Abstract: Disclosed are a method of preparing conjugated diene and a device therefor. More particularly, disclosed a method of preparing conjugated diene, wherein generated gas including butadiene is cooled and then water discharged at a lower part is not directly treated as waste water and subjected to byproduct removal and steam-extraction to utilize converted steam, and an installation issue of an existing biological waste water disposal equipment due to an excessive amount of byproducts can be resolved, and a device therefor are disclosed.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 15, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Sang Jin Han, Jun Han Kang, Dong Hyun Ko, Hyun Seok Nam, Joo Hyuck Lee, Jun Kyu Han, Myung Ji Suh, Kyong Yong Cha, Dae Heung Choi, Ye Seul Hwang
  • SEMICONDUCTOR PACKAGES
    Publication number: 20180122772
    Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.
    Type: Application
    Filed: April 27, 2017
    Publication date: May 3, 2018
    Inventors: KEUNG BEUM KIM, HYUNJONG MOON, SEUNG-YONG CHA
  • Bismuth molybdate-based catalyst having zeolite coating layer, method of preparing the same, and method of preparing 1,3-butadiene using the same
    Patent number: 9925525
    Abstract: The present invention relates to a bismuth molybdate-based composite oxide catalyst having a microporous zeolite coating layer on the surface thereof and thus having high selectivity for 1,3-butadiene, a method of preparing the same, and a method of preparing 1,3-butadiene using the same. The catalyst has a microporous zeolite coating layer, and thus enables only gaseous products (light) to selectively pass through the zeolite coating layer, improving selectivity for 1,3-butadiene.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 27, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Dae Heung Choi, Dong Hyun Ko, Jun Han Kang, Kyong Yong Cha, Dae Chul Kim, Joo Hyuck Lee, Hyun Seok Nam, Myung Ji Suh, Ye Seul Hwang, Jun Kyu Han, Sang Jin Han
  • Composite oxide catalyst for preparing butadiene and method of preparing the same
    Patent number: 9884315
    Abstract: Disclosed are a composite oxide catalyst for preparing butadiene and a method of preparing the same. More particularly, a composite oxide catalyst, for preparing butadiene, including a metal composite oxide and AlPO4, and a method of preparing the same are disclosed. According to the present disclosure, a composite oxide catalyst for preparing butadiene, which includes a specific binder material, prevents generation of ingredients with a high boiling point, has superior catalyst strength, catalytic activity and butadiene yield, and a method of preparing the same are provided.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 6, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Myung Ji Suh, Kyong Yong Cha, Dae Heung Choi, Ye Seul Hwang, Dong Hyun Ko
  • SEMICONDUCTOR DEVICE
    Publication number: 20180006047
    Abstract: A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.
    Type: Application
    Filed: September 19, 2017
    Publication date: January 4, 2018
    Inventor: Jae Yong CHA
  • Semiconductor memory device for improving signal integrity issue in center pad type of stacked chip structure
    Patent number: 9830973
    Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keung Beum Kim, HyunJong Moon, Heeseok Lee, Seung-Yong Cha
  • Semiconductor packages including thermal blocks
    Patent number: 9799591
    Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Yong Cha, Keung Beum Kim, Yonghoon Kim, HyunJong Moon, Heeseok Lee
  • SEMICONDUCTOR MEMORY DEVICE FOR IMPROVING SIGNAL INTEGRITY ISSUE IN CENTER PAD TYPE OF STACKED CHIP STRUCTURE
    Publication number: 20170301392
    Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Inventors: Keung Beum Kim, HyunJong Moon, Heeseok Lee, Seung-Yong Cha
  • Mesoporous composite oxide catalyst, method for preparing the same and method for synthesizing 1,3-butadiene using the same
    Patent number: 9782765
    Abstract: Disclosed are a mesoporous composite oxide catalyst, a method for preparing the same and a method for synthesizing 1,3-butadidne using the same. The surface area is increased by introducing certain porous silica into preparation of a catalyst for synthesizing 1,3-butadiene, thereby improving a conversion ratio of normal-butene, and selectivity and yield of 1,3-butadiene, and providing economic efficiency from the viewpoint of decreasing an amount of used metal and reducing catalyst production cost.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 10, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Myung Ji Suh, Dong Hyun Ko, Kyong Yong Cha, Jun Han Kang, Dae Chul Kim, Hyun Seok Nam, Dae Heung Choi