Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A housing type golf simulation apparatus and features the housing that the internal space is available having front, rear, upper and left/right side; monitor installation section which is provided backward in the rear side direction from the said front housing so that the monitor can be seated in the said front housing; golf simulation computer which is provided in the said internal space; and the monitor to be seated in the said monitor installation section. Thus, it is advantageous to implement various additional functions in the housing while installing, managing and moving the entire golf simulation apparatus in an integrated module.

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract: A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate. A second semiconductor package is provided on the circuit substrate and spaced apart from the first semiconductor package. An insulating electromagnetic shielding structure is provided on the top and the lateral surfaces of the first semiconductor package. A conductive electromagnetic shielding structure is provided on the circuit substrate to cover the first and second semiconductor packages and the insulating electromagnetic shielding structure.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract: An insulated wire, which is coated, on a conductor, with a thin-film insulating layer composed of a resin dispersion, wherein the resin dispersion contains: a polyester-series resin (A) in a continuous phase; and a resin (B) having a functional group capable of reacting with the polyester-series resin, and, if necessary, an olefin-series resin (C), in a dispersed phase; and the resin dispersion.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract: A video encoding/decoding method and apparatus select a prediction mode set based on neighboring pixels and, in some embodiments, obviate the need to encode additional information for selecting a prediction mode set and thereby improve the performance of compression.

Abstract: A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

Abstract: A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal.

Abstract: A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

Abstract: An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.

Abstract: A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

Abstract: A method for preventing or treating a bone disease, includes administering to a patient having the bone disease a pharmaceutical composition comprising glyceollin as an active ingredient. The active ingredient, glyceollin promotes degradation of the Runx2 protein in osteoblasts and inhibits the mRNA expression of Rankl in osteoblasts to prevent the differentiation of osteoclasts. Furthermore, glyceollin is capable of ameliorating osteoporosis in animal models for osteoporosis. The composition promises drug or food for prevention or treatment of not only osteoporosis but also bone diseases caused by cancer metastatic to the bone.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.