Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract: A keyboard-input information-security apparatus and method are provided.

Abstract: A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode.

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.

Abstract: Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device.

Abstract: An embedded chip-on-chip package comprises a printed circuit board having a recessed semiconductor chip mounting unit, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit, and a second semiconductor chip mounted on the first semiconductor chip and the printed circuit board.

Abstract: An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit.

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.

Abstract: An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.

Abstract: A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal.

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract: Provided are a light, thin, short and small, and multi-functional anisotropic particle-arranged structure including two electrodes having fine pitches that are repeatedly compressed to be connected to external elements, and a method of manufacturing the anisotropic particle-arranged structure. The anisotropic particle-arranged structure includes an elastic polymer layer, and elastic conductors or elastic thermal conductors formed in the elastic polymer layer so that upper and lower portions of the elastic conductors or elastic thermal conductors are exposed.

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract: An optical system and an SSD module that maintain optimal SI, PI and EMI characteristics without a shield based on a ground voltage and an impedance match. The optical system includes a solid state drive (SSD) module and an input/output (I/O) interface. The SSD module includes a plurality of solid state memory units. The input/output (I/O) interface receives data to be written to at least one of the solid state memory units from a main memory unit, the input/output (I/O) interface transmits data written in at least one of the solid state memory units to the main memory unit. The SSD module and the I/O interface transmit and receive data using an optical medium.

Abstract: A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit.

Abstract: A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit.