Patents by Inventor Yong Hwan Kwon

Yong Hwan Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070010041
    Abstract: Example embodiments of the present invention relate to a method of manufacturing an optical device having a transparent cover and a method of manufacturing an optical device module using the optical device. According to an example method of manufacturing the optical device, a semiconductor substrate having a plurality of dies including an effective pixel and a plurality of bonding pads arranged around the effective pixel is prepared. A protective layer may be formed on the semiconductor substrate to selectively cover the effective pixel. An adhesive pattern may be formed to enclose an edge of the effective pixel, and a transparent cover may be attached to correspond to the effective pixel using the adhesive pattern.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 11, 2007
    Inventors: Suk-Chae Kang, Yong Kwon, Yong-Hwan Kwon, Gu-Sung Kim, Sun-Wook Heo
  • Publication number: 20060236339
    Abstract: A method is provided for controlling a television including a user input part for manipulating a channel adjusting item. The method includes displaying a channel map showing a predetermined number of channels including a tuned broadcast channel if the channel adjusting item is selected through the user input part, and a channel setting information menu corresponding to one of the channels shown in the channel map. Thus, the television control method not only allows a user to easily and simply recognize a channel setting state according to channels when the user wants to adjust channel-related functions, but also allows a user to conveniently and effectively adjust the channel setting state according to the channels.
    Type: Application
    Filed: February 21, 2006
    Publication date: October 19, 2006
    Inventors: Jung-dae Kim, Yong-hwan Kwon, Sun-hwa Shin
  • Patent number: 7115483
    Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: October 3, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Hwan Kwon, Se Yong Oh, Sa Yoon Kang
  • Publication number: 20060202334
    Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.
    Type: Application
    Filed: June 1, 2006
    Publication date: September 14, 2006
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan KWON, Sa-Yoon Kang, Chung-Sun Lee
  • Publication number: 20060174272
    Abstract: A video processing apparatus including a memory to store a plurality of character strings corresponding a plurality of channels in predetermined sequence, a display part to display the character string to be superposed on a picture of the corresponding channel, a signal receiver to receive a forward or backward change signal for the character string in accordance with selection of a user, and a channel selection controller to control the display part to display a character string previously or next to the character string of the channel being currently displayed such that the previous or next character string is superposed on the picture of the corresponding channel, when the signal receiver receives the forward or backward change signal for the character string. Thus, a user can easily and quickly select a desired channel from among a plurality of channels. Also, a user can select a desired channel through simple, convenient and small user interface.
    Type: Application
    Filed: November 30, 2005
    Publication date: August 3, 2006
    Inventor: Yong-hwan Kwon
  • Patent number: 7078331
    Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: July 18, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Kwon, Sa-Yoon Kang, Chung-Sun Lee
  • Patent number: 7074704
    Abstract: A bump of a semiconductor chip comprises a plurality of bond pads formed on a semiconductor chip, a conductive bump formed on the bond pads; and a sidewall insulating layer formed on sidewalls of the conductive bump. It is possible for the semiconductor chip to prevent electrical shorts and improve productivity even though a pitch of bond pad is decreased.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: July 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hwan Kwon, Sa-yoon Kang
  • Publication number: 20060091504
    Abstract: In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium alloy layer formed on the inner lead to produce an inter-metallic compound layer of AuxSn composition during the bump bonding process.
    Type: Application
    Filed: October 21, 2005
    Publication date: May 4, 2006
    Inventors: Un-Byoung Kang, Chung-Sun Lee, Sa-Yoon Kang, Yong-Hwan Kwon
  • Publication number: 20060071303
    Abstract: Embodiments of the present invention are directed to a film substrate of a semiconductor package. The film substrate of the semiconductor package comprises a thin film insulating substrate and a thin copper circuit pattern. An inter-pattern groove between the thin copper circuit patterns is formed by laser etching. Accordingly, the embodiment improves electrical contact between the film substrate and a semiconductor chip mounted thereon, and improves the manufacturing process for the film substrate by adopting a simple laser machining to form the thin copper circuit pattern in lieu of a traditional wet-etching process that undergoes complex lithography steps.
    Type: Application
    Filed: August 31, 2005
    Publication date: April 6, 2006
    Inventors: Chung-Sun Lee, Yong-Hwan Kwon, Sa-Yoon Kang, Kyoung-Sei Choi
  • Patent number: 7005687
    Abstract: The present invention provides the photodetector comprising a lower cladding layer including a n-type doped region, an absorbing layer, an upper cladding layer including a p-type doped region, and ohmic electrodes connected to said lower cladding layer and said upper cladding layer, wherein said p-type doped region extends to be formed into said absorbing layer by a predetermined length. In accordance with present invention, by reducing effect of the hetero junction barrier where holes move in the intrinsic region, the operating voltage can be decreased and the bandwidth can be improved.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: February 28, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joong Seon Choe, Yong Hwan Kwon
  • Publication number: 20060003568
    Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.
    Type: Application
    Filed: March 21, 2005
    Publication date: January 5, 2006
    Inventors: Kyoung-Sei Choi, Sa-Yoon Kang, Yong-Hwan Kwon, Chung-Sun Lee
  • Publication number: 20050285277
    Abstract: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 29, 2005
    Inventors: Yong-Hwan Kwon, Sa-Yoon Kang, Chung-Sun Lee, Kyoung-Sei Choi
  • Publication number: 20050205524
    Abstract: A method of manufacturing a tape wiring substrate, by which the production cost can be reduced by a simplified manufacturing process. A fine wiring pattern having fine pitches can be formed. The method of manufacturing a tape wiring substrate includes preparing a base film, forming a metal layer on the base film, and processing the metal layer into a wiring pattern using a laser. In addition, the metal layer is partially removed using the laser, and a wiring pattern is formed by a subsequent wet etching.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 22, 2005
    Inventors: Chung-Sun Lee, Sa-Yoon Kang, Yong-Hwan Kwon, Kyoung-Sei Choi
  • Publication number: 20050017343
    Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 27, 2005
    Inventors: Yong-Hwan Kwon, Sa-Yoon Kang, Chung-Sun Lee
  • Publication number: 20040251546
    Abstract: A chip package including at least one interconnection lead, composed of at least one first metal, at least one bump, a surface of which is plated with at least one second metal with a melting point lower than the first metal, and a eutectic alloy, composed of the at least one first metal and the at least one second metal, that at least electrically connects the interconnection lead and the bump and a method of manufacturing a chip package.
    Type: Application
    Filed: February 17, 2004
    Publication date: December 16, 2004
    Inventors: Si-Hoon Lee, Sa-Yoon Kang, Dong-Han Kim, Yong-Hwan Kwon, Chung-Sun Lee
  • Patent number: 6818998
    Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 16, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Hwan Kwon, Se Yong Oh, Sa Yoon Kang
  • Publication number: 20040219715
    Abstract: A bump of a semiconductor chip comprises a plurality of bond pads formed on a semiconductor chip, a conductive bump formed on the bond pads; and a sidewall insulating layer formed on sidewalls of the conductive bump. It is possible for the semiconductor chip to prevent electrical shorts and improve productivity even though a pitch of bond pad is decreased.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 4, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Kwon, Sa-Yoon Kang
  • Publication number: 20040118992
    Abstract: The present invention provides the photodetector comprising a lower cladding layer including a n-type doped region, an absorbing layer, an upper cladding layer including a p-type doped region, and ohmic electrodes connected to said lower cladding layer and said upper cladding layer, wherein said p-type doped region extends to be formed into said absorbing layer by a predetermined length.
    Type: Application
    Filed: October 8, 2003
    Publication date: June 24, 2004
    Inventors: Joong Seon Choe, Yong Hwan Kwon
  • Publication number: 20040120648
    Abstract: Disclosed herein are a SSC integrated optical device and a method of manufacturing the same. When a taper waveguide in a SSC region is formed, a width and a thickness are controlled exactly by means of a selective wet etch method. In particular, a start portion of the taper waveguide is formed to have a mesa structure or a reverse-mesa structure. Accordingly, it is possible to control process parameters reproducibly, reduce the cost for an optical alignment and improve an optical coupling efficiency and quantum efficiency remarkably.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 24, 2004
    Inventors: Yong Hwan Kwon, Joong Seon Choe, Ki Soo Kim
  • Publication number: 20030214035
    Abstract: A bump of a semiconductor chip comprises a plurality of bond pads formed on a semiconductor chip, a conductive bump formed on the bond pads; and a sidewall insulating layer formed on sidewalls of the conductive bump. It is possible for the semiconductor chip to prevent electrical shorts and improve productivity even though a pitch of bond pad is decreased.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 20, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Kwon, Sa-Yoon Kang