Abstract: A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract: Silver-tin alloy solder bumps are fabricated by forming a masked underbump metallurgy layer on a microelectronic substrate, to define exposed portions of the underbump metallurgy layer, plating silver on the exposed portions of the underbump metallurgy, plating tin on the silver and reflowing to form silver-tin alloy solder bumps. Accordingly, silver-tin alloy is not plated. Rather, individual layers of silver and tin are plated, and then reflowed to form silver-tin alloy solder bumps.

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate.

Abstract: A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate.

Abstract: Silver-tin alloy solder bumps are fabricated by forming a masked underbump metallurgy layer on a microelectronic substrate, to define exposed portions of the underbump metallurgy layer, plating silver on the exposed portions of the underbump metallurgy, plating tin on the silver and reflowing to form silver-tin alloy solder bumps. Accordingly, silver-tin alloy is not plated. Rather, individual layers of silver and tin are plated, and then reflowed to form silver-tin alloy solder bumps.