Patents by Inventor Yong-Ju Kim

Yong-Ju Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Majority decision circuit
    Patent number: 9054697
    Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
  • SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME
    Publication number: 20150124545
    Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.
    Type: Application
    Filed: May 15, 2014
    Publication date: May 7, 2015
    Applicant: SK hynix Inc.
    Inventors: Yong-Ju KIM, Dae-Han KWON, Hae-Rang CHOI, Jae-Min JANG
  • Duty cycle correction circuit and operation method thereof
    Patent number: 9018994
    Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Shin-Deok Kang, Jae-Min Jang, Yong-Ju Kim, Hae-Rang Choi
  • Data recovery circuit and operating method thereof
    Patent number: 9018991
    Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: April 28, 2015
    Assignees: SK Hynix Inc., Industry-University Cooperation Foundation Hanyang University
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
  • SEMICONDUCTOR MEMORY DEVICE HAVING PADS
    Publication number: 20150076614
    Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventors: Chang Kun PARK, Seong Hwi SONG, Yong Ju KIM, Sung Woo HAN, Hee Woong SONG, Ic Su OH, Hyung Soo KIM, Tae Jin HWANG, Hae Rang CHOI, Ji Wang LEE, Jae Min JANG
  • SEMICONDUCTOR MEMORY DEVICE HAVING PADS
    Publication number: 20150076703
    Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventors: Chang Kun PARK, Seong Hwi SONG, Yong Ju KIM, Sung Woo HAN, Hee Woong SONG, Ic Su OH, Hyung Soo KIM, Tae Jin HWANG, Hae Rang CHOI, Ji Wang LEE, Jae Min JANG
  • PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    Publication number: 20150054558
    Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.
    Type: Application
    Filed: November 27, 2013
    Publication date: February 26, 2015
    Applicant: SK hynix Inc.
    Inventors: Jae Min JANG, Yong Ju KIM, Dae Han KWON, Kil Ho CHA
  • COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT
    Publication number: 20150043702
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Dae-Han KWON, Yong-Ju KIM, Jae-Il KIM, Taek-Sang SONG
  • DATA RECOVERY CIRCUIT AND OPERATING METHOD THEREOF
    Publication number: 20150042387
    Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
    Type: Application
    Filed: December 15, 2013
    Publication date: February 12, 2015
    Applicants: Industry-University Cooperation Foundation Hanyang University, SK hynix Inc.
    Inventors: Hae-Rang CHOI, Yong-Ju KIM, Oh-Kyong KWON, Kang-Sub KWAK, Jun-Yong SONG, Hyeon-Cheon SEOL
  • Semiconductor memory device having pads
    Patent number: 8916975
    Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Kun Park, Seong Hwi Song, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang
  • Counting circuit of semiconductor device and duty correction circuit of semiconductor device using the same
    Patent number: 8866526
    Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim
  • Counting circuit, delay value quantization circuit, and latency control circuit
    Patent number: 8867698
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dae-Han Kwon, Yong-Ju Kim, Jae-Il Kim, Taek-Sang Song
  • Latency control circuit and semiconductor device including the circuit
    Patent number: 8837239
    Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 16, 2014
    Assignees: SK Hynix Inc., University of Seoul Industry Cooperation Foundation
    Inventors: Jong Gon Jung, Yong Sam Moon, Yong Ju Kim, Jong Ho Jung
  • Delay circuit and semiconductor apparatus including the same
    Patent number: 8823431
    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Min Jang, Yong Ju Kim, Dae Han Kwon, Hae Rang Choi
  • Clock generation circuit and semiconductor apparatus including the same
    Patent number: 8816734
    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Min Jang, Yong Ju Kim, Dae Han Kwon, Hae Rang Choi
  • On-die termination circuit
    Patent number: 8810274
    Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Ju Kim, Hyung Soo Kim, Hae Rang Choi, Jae Min Jang
  • LENS FOR CONTROLLING ILLUMINANCE DISTRIBUTION AND LIGHT-EMITTING DIODE PACKAGE INCLUDING THE LENS
    Publication number: 20140204591
    Abstract: A lens for controlling an illuminance distribution to realize high luminous flux efficiency by maintaining a required beam angle and uniformity on an illumination surface having a particular shape, such as a square shape, and a light-emitting diode (LED) package including the lens are provided. The lens includes an incidence surface onto which light emitted from a light-emitting device is incident, and an emission surface through which the light incident onto the incidence surface is emitted. An illuminance controller, which includes at least two optical devices, is disposed on the emission surface to control an illuminance distribution of the emission surface.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-ju KIM, Sang-woo HA, Chin-woo KIM, Jin-ha KIM
  • Device for generating reset signal having sufficient pulse width
    Patent number: 8773180
    Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Min Jang, Yong Ju Kim, Dan Han Kwon, Hae Rang Choi
  • DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF
    Publication number: 20140184294
    Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
    Type: Application
    Filed: March 16, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Shin-Deok KANG, Jae-Min JANG, Yong-Ju KIM, Hae-Rang CHOI
  • Delay control circuit and clock generation circuit including the same
    Patent number: 8754686
    Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: June 17, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dae Han Kwon, Yong Ju Kim, Jae Min Jang, Hae Rang Choi