Patents by Inventor Yong-Ju Kim

Yong-Ju Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP
    Publication number: 20140132339
    Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: SK hynix Inc.
    Inventors: Dae-Han KWON, Yong-Ju KIM, Taek-Sang SONG
  • COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20140103981
    Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: SK hynix Inc.
    Inventors: Hae-Rang CHOI, Yong-Ju KIM
  • Phase locked loop
    Patent number: 8686768
    Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Jae-Min Jang
  • SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF
    Publication number: 20140068112
    Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.
    Type: Application
    Filed: December 10, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventors: Hae-Rang CHOI, Yong-Ju KIM, Dae-Han KWON, Jae-Min JANG
  • Filtering circuit, phase identity determination circuit and delay locked loop
    Patent number: 8664987
    Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 4, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dae-Han Kwon, Yong-Ju Kim, Taek-Sang Song
  • Integrated circuit chip and transmitting /receiving system including the same
    Patent number: 8633762
    Abstract: A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Ju Kim, Dae-Han Kwon, Hae-Rang Choi, Jae-Min Jang
  • LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE CIRCUIT
    Publication number: 20140010029
    Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.
    Type: Application
    Filed: March 12, 2013
    Publication date: January 9, 2014
    Inventors: Jong Gon JUNG, Yong Sam MOON, Yong Ju KIM, Jong Ho JUNG
  • Counting circuit of semiconductor device and duty correction circuit of semiconductor device using the same
    Patent number: 8625734
    Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: January 7, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim
  • DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    Publication number: 20140002154
    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.
    Type: Application
    Filed: December 12, 2012
    Publication date: January 2, 2014
    Applicant: SK hynix Inc.
    Inventors: Jae Min JANG, Yong Ju KIM, Dae Han KWON, Hae Rang CHOI
  • SEMICONDUCTOR APPARATUS AND TEST CIRCUIT THEREOF
    Publication number: 20140003161
    Abstract: A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 2, 2014
    Applicant: SK HYNIX INC.
    Inventors: Jong Ho SON, Yong Ju KIM
  • CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    Publication number: 20140002149
    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.
    Type: Application
    Filed: December 12, 2012
    Publication date: January 2, 2014
    Applicant: SK hynix Inc.
    Inventors: Jae Min JANG, Yong Ju KIM, Dae Han KWON, Hae Rang CHOI
  • DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME
    Publication number: 20130342250
    Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.
    Type: Application
    Filed: December 12, 2012
    Publication date: December 26, 2013
    Applicant: SK HYNIX INC.
    Inventors: Dae Han KWON, Yong Ju KIM, Jae Min JANG, Hae Rang CHOI
  • RESET SIGNAL GENERATION APPARATUS
    Publication number: 20130342245
    Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.
    Type: Application
    Filed: December 19, 2012
    Publication date: December 26, 2013
    Applicant: SK HYNIX INC.
    Inventors: Jae Min JANG, Yong Ju KIM, Dae Han KWON, Hae Rang CHOI
  • Integrated circuit
    Patent number: 8610475
    Abstract: An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Ju Kim, Seong-Jun Lee, Hae-Rang Choi, Jae-Min Jang
  • MAJORITY DECISION CIRCUIT
    Publication number: 20130249593
    Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
    Type: Application
    Filed: May 9, 2013
    Publication date: September 26, 2013
    Applicant: SK hynix Inc.
    Inventors: Hae-Rang CHOI, Yong-Ju KIM, Oh-Kyong KWON, Kang-Sub KWAK, Jun-Yong SONG, Hyeon-Cheon SEOL
  • Semiconductor integrated circuit and method for driving the same
    Patent number: 8542044
    Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Ju Kim, Dae-Han Kwon, Hae-Rang Choi, Jae-Min Jang
  • ELECTRON MICROSCOPE SYSTEM USING AUGMENTED REALITY
    Publication number: 20130221218
    Abstract: Provided is an electron microscope system using an augmented reality in that it recognizes a sample identification information by using an observation image generated through an electron microscope and the observation image is linked with the pre-set sample information according to the recognized sample identification information, so that an augmented reality image thereof is provided, thereby even the unskilled man can easily utilize the electron microscope and it can generate excitement about an education thereof.
    Type: Application
    Filed: January 23, 2013
    Publication date: August 29, 2013
    Inventors: Jun-Hee LEE, Yong-Ju KIM
  • COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT
    Publication number: 20130216017
    Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 22, 2013
    Inventors: Dae-Han KWON, Yong-Ju Kim, JAE-IL Kim, Taek-Sang Song
  • Majority decision circuit
    Patent number: 8476924
    Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 2, 2013
    Assignees: Hynix Semiconductor Inc., Industry-University Cooperation Foundation Hanyang University
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
  • FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP
    Publication number: 20130162311
    Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
    Type: Application
    Filed: September 7, 2012
    Publication date: June 27, 2013
    Inventors: Dae-Han KWON, Yong-Ju Kim, Taek-Sang Song