Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Abstract: A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.

Abstract: A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.

Abstract: An image forming apparatus includes a transfer unit to transfer a toner to a printing medium, and a waste toner recovery unit to convey a waste toner recovered from the transfer unit. A first driving source for driving the transfer unit is configured independently of a second driving source for driving the waste toner recovery unit, so that deterioration in the quality of image caused by the waste toner recovery unit can be minimized.

Abstract: A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.

Abstract: Disclosed herein too is a method that includes dispersing nanotubes in media that comprises flavin moieties substituted with solubilizing side chains, and/or non-flavin containing molecular species; self-assembling the flavin moieties and other non-flavin containing molecular species in a pattern that is orderly wrapped around the nanotubes to form a composite; introducing desired amounts of an optional reagent that competes with self-assembly in order to disturb the wrapping around nanotubes with moderate order; and centrifuging the mass of the nanotubes and the composites to extract the composite from other nanotubes that are not in composite form.

Abstract: An image forming apparatus capable of reducing a space required to install a transfer unit to achieve a compact body size. The image forming apparatus can include a body, a frame installed in the body, a transfer unit installed inside the frame, and a waste toner recovery device to recover waste toner collected from the transfer unit. The waste toner recovery device can include a first delivery unit to deliver the waste toner in a first direction, and a second delivery unit to deliver the waste toner, delivered from the first delivery unit, in a second direction. The second delivery unit can be movably installed to the frame and can be coupled to or detached from the first delivery unit via movement thereof.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.

Abstract: A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.

Abstract: A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.

Abstract: A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.

Abstract: Disclosed herein is a method of preparing an antithrombotic agent from muskrat musk and an antithrombotic agent having a high potency obtained therefrom, wherein the antithrombotic agent is prepared by treating muskrat musk with ethanol to obtain an ethanol extract; carrying out two normal phase column chromatographies while raising the combination ratio of hexane and ethyl acetate to obtain numerous fractions; carrying out thin layer chromatographies and identifying the material patterns of the fractions with UV lamps and 10% sulfuric acid to divide the materials which have a similar moving distance into groups; measuring a thrombin time of each group to isolate a group having a potent antithrombotic activity; carrying out a reverse phase column chromatography while raising the combination ratio of acetonitrile and water to obtain numerous fractions; and isolating an antithrombotic agent material having a high potency therefrom.

Abstract: A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.

Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.

Abstract: An image forming apparatus and a transfer device thereof are disclosed. The transfer device includes an intermediate transfer belt, at least one intermediate transfer belt roller to maintain tension in the intermediate transfer belt, transfer rollers to press the intermediate transfer belt to image carriers and a state changing device to change an operating state between at least a first state, in which the tension in the intermediate transfer belt is released, and a second state, in which select ones of the transfer rollers are separated from the intermediate transfer belt.

Abstract: A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.

Abstract: A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.