Abstract: A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.

Abstract: A method, apparatus, and medium of converting a two-dimensional (2D) image to a three-dimensional (3D) image based on visual attention are provided. A visual attention map including visual attention information, which is information about a significance of an object in a 2D image, may be generated. Parallax information including information about a left eye image and a right eye image of the 2D image may be generated based on the visual attention map. A 3D image may be generated using the parallax information.

Abstract: A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver uni

Abstract: A method, apparatus, and medium of generating a visual attention map. A visual attention map to extract visual attention may be generated to convert a two-dimensional (2D) image into a three-dimensional (3D) image based on visual attention. The 2D image may be downscaled and at least one downscaled image may be generated. A feature map may be extracted from the 2D image and the at least one downscaled image, and the visual attention map may be generated.

Abstract: Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.

Abstract: A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.

Abstract: A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.

Abstract: A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

Abstract: The present invention relates to a system for transmitting and receiving audio, particularly, to a method and apparatus for transmitting and receiving of object-based audio contents, which packetizes audio objects having the same characteristic. To achieve the above, the present invention includes filtering a plurality of ESs according to common information, adding a packet header to the respective filtered ESs and generate ES packets, aggregating all the generated ES packets and then adding a multi-object packet header to the aggregated ES packets to generate an object packet, and multiplexing the generated object packet, packetizing the multiplexed object packet according to a transmitting media and transmitting the packetized object packet.

Abstract: A transfer unit and an image forming apparatus having the same. The transfer unit includes a transfer unit body to accommodate a printing medium conveyor, which makes a printing medium receive an image while moving the printing medium, a body handle used to mount the transfer unit body in an image forming apparatus and to separate the transfer unit body from the image forming apparatus, and a locking and releasing unit to lock the transfer unit body to the image forming apparatus and to release a locking connection therebetween. The locking and releasing unit is disposed to carry out a releasing operation by grasping the body handle.

Abstract: A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

Abstract: Provided are a method of tuning a coding rate and applying an unequal error protection for an adaptive video transmission, and a video transmission/reception apparatus using the method. The video transmission apparatus may include: a coding rate tuner to predict, as a channel capacity of a subsequent channel interval, an estimated channel capacity value fed back from the video reception apparatus, and to tune video and channel coding rates within the predicted channel capacity; a video encoder to perform video encoding of video frames at the tuned video coding rate, and to generate a video packet; and a forward error correction (FEC) encoder to apply the unequal error protection based on a length of the video packet and a type of the video frames included in the video packet, and to perform channel encoding of the video packet at the tuned channel coding rate to generate a bitstream.

Abstract: Provided are an apparatus and method for coding and decoding a multi-object audio signal. The apparatus includes a down-mixer for down-mixing the audio signals into one down-mixed audio signal and extracting supplementary information including header information and spatial cue information for each of the audio signals, a coder for coding the down-mixed audio signal, and a supplementary information coder for generating the supplementary information as a bit stream. The header information includes identification information for each of the audio signals and channel information for the audio signals.

Abstract: A developing apparatus usable with an image forming apparatus includes a developer receptacle having a sidewall on which a shaft hole is formed, a rotation shaft having a length shorter than a distance between opposite sidewalls of the developer receptacle and an end on which a connection hole is formed, and a driving member rotatably supported by the shaft hole of the developer receptacle and having a connecting shaft inserted into the connection hole of the rotation shaft.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Abstract: Provided are a gas storage structure and a gas storage apparatus including the gas storage structure. The gas storage structure includes a gas storage part including an opening thereon and an entrance control part disposed on the opening and including a gate.

Abstract: Disclosed are an apparatus and a method of providing contents. The apparatus of providing the contents may include a receiving unit to receive, from a contents provider, contents and information about a contents providing location, a local group setting unit to search for at least one cell based on the information about the contents providing location and to set the retrieved cell as a content providing location group of the contents, and a transmitting unit to transmit the contents to the set content providing location group. The object based audio contents may be consecutively replayed based on an identical audio preset.

Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.