Abstract: An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines.

Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Abstract: There is provided a transformer including cores combined with a bobbin wound with coils, and center leg parts extended from the cores and contacting each other by being inserted into both ends of the bobbin, wherein stress dispersion hole, dispersing stress occurring according to temperature variations around the cores, is formed at the edge of center leg connection parts of the cores from which the center leg parts are extended.

Abstract: A liquid crystal display device includes: a liquid crystal panel; a horizontal sync signal having a horizontal period; a gate driver that supplies a plurality of gate signals sequentially to a plurality of gate lines, wherein a first gate line provides a gate signal with a gate pulsewidth equal to the horizontal period +? and a second gate line provides a gate signal with a gate pulsewidth equal to the horizontal period +? so that gates signals on the first and second gate lines overlay by 2? and wherein the first and second gate lines are adjacent to one another; and a data driver that supplies pixel data signals to a plurality of data lines on the liquid crystal panel during every period of the horizontal sync signals.

Abstract: Disclosed is an image conversion device and method converting a two-dimensional (2D) image into a three-dimensional (3D) image. The image conversion device may selectively adjust illumination within the 2D image, generate a disparity map for the illumination adjusted image, and selectively adjust a depth value of the disparity map based on edge discrimination.

Abstract: A local multi-view image display apparatus and method is provided. The local multi-view image display method may track a location of an observer, and locally display a multi-view input image on the tracked location.

Abstract: A three-dimensional (3D) image generation apparatus and method using a region extension of an object in a depth map is provided. The 3D image generation apparatus may include a discontinuity preservation smoothing filtering unit to apply a discontinuity preservation smoothing filter preserving discontinuity of a boundary or a shape of a depth image, a boundary preservation filtering unit to apply a max filter to a depth image for increasing a depth value of an object, and a rendering unit to render a two-dimensional (2D) color image and the filtered depth image and to generate a 3D image.

Abstract: Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.

Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

Abstract: A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.

Abstract: A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.

Abstract: The present invention relates to a method of systematically and synthetically accessing modality conversion that is an important part in the contents adaptive conversion process of a universal multimedia access system. The present invention provides an effective method of solving a problem, which is incurred at the time of modality conversion and still remains as one of difficult problems incurred during adaptive contents conversion. For this purpose, the present invention includes overlapped contents modeling newly proposed to determine modality conversion, a method of flexibly and clearly expressing and applying user preference for the modality conversion, and a resource allocation method of distributing resources among complicated contents based on the user preference. As a result, the integration of the above three methods provides a synthetic solution, particularly, to a problem incurred in the modality conversion and, generally, to a problem incurred in the adaptive conversion of contents.

Abstract: A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.

Abstract: A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.

Abstract: A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.

Abstract: A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.

Abstract: An apparatus and method for accurately determining whether or not to perform display switching in a portable terminal. The apparatus includes a controller for sensing an input for display switching, giving weights to a plurality of elements for display switching, combining the elements given the weights, judging whether to display switch or not dependent on a user's probable intention, and processing to switch a display.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.

Abstract: A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.