Abstract: The present invention provides a novel structure for sealing a cosmetic container using a double-injection molded rib on the container body sealing against a deformable hard-rubber ring on the container cover. The invention will maximize product reliability by improving the sealing structure of a make-up base or cosmetic container through providing a clear, air-tight effect since the sealing structure cannot be deformed, even in the case of long-term use. The invention provides uniform, airtight adhesion without unequal distribution of coupling intensity between internal sealing components when the container cover is closed. Further, the aesthetics of the container are increased because a closure clasp is not necessary, and it is possible to eliminate the problem of dried-out product created when the container is fitted with a closure clasp or similar device.

Abstract: Disclosed is a lead frame base plate for a light emitting device, the base plate including: one or more lead frame areas respectively including a plurality of lead frames repeated in a first direction, the lead frame areas being arranged in parallel to be spaced apart from each other in a second direction intersecting with the first direction; and two or more openings extended in the first direction at both sides of each lead frame area so that the plurality of lead frames may be divided through a single direction sawing process performed in the second direction.

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract: The present invention can magnify a sealing characteristic and prevent deformation of hard rubber by coupling a container body with a rib formed on an external cap and through double-injection molding by an elastomer having a different elastic restoring force from the hard rubber charged and hardened in an injection concave groove of a support body that accommodates an internal container, in order to maximize product reliability by improving a sealing structure of a make-up base container or a cosmetic container and providing a clear air-tight effect since the sealing structure cannot be transformed even in case of long-term use.

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract: A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device.

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract: In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.

Abstract: A web browsing method and apparatus for enhancing a user's convenience in web browsing is provided in a system that uses a multi-core processor. The web browsing method and apparatus is applicable in a system, such as a smart phone that has a low computing power or that has a storage device like a flash memory operating in a rapid manner. Optimized machine codes are stored in files and incremental optimization is achieved, so the JAVASCRIPT® program of the web application has a small compilation overhead and achieves fast execution.

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract: The present invention relates to a dispenser for supplying a disposable paper product of a roll type such as a toilet paper, a hand towel and etc. The dispenser comprises a main body casing which accommodates the paper product and has a rotating shaft supporting the paper product to be rotatable and a discharging part for discharging the paper product, and a wet type cutting unit which is located at the discharging part to provide liquid to a part of the paper product that is to be cut. According to the present invention, liquid is provided to an area of the paper product to be cut, so that the paper product can be easily cut with a relatively small force.

Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract: A capacitor of a semiconductor device and a method for manufacturing the same includes a lower metal layer on and/or over a semiconductor substrate; an insulating layer formed on and/or over the lower metal layer with step difference; and an upper electrode on and/or over the insulating layer pattern, wherein a top corner of the upper electrode is rounded so that a curvature pattern is formed on the top corner of the upper electrode.

Abstract: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate.