Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: The present invention relates to a pharmaceutical preparation comprising a granule comprising a compound of Chemical Formula 1 or a pharmaceutically acceptable salt thereof, and a diluent. The pharmaceutical preparation has a high productivity of the preparation due to excellent tableting properties, friability, and mass uniformity. The pharmaceutical preparation has low generated amount of impurities and high stability.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: Disclosed are an interfacing method and an apparatus for three-dimensional (3D) sketch. According to an example embodiment, the interfacing method for sketching in a virtual space of three dimensions includes determining a surface including an area in which a first user input is received in the virtual space to be a region of interest, controlling a position of the region of interest in the virtual space based on a second user input on the region of interest, and generating at least one sketch line belonging to the region of interest based on a third user input.

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

Abstract: An electronic device in a neighbor awareness networking (NAN) cluster is provided. The electronic device includes a wireless fidelity (Wi-Fi) transceiver; and a processor, coupled with the Wi-Fi transceiver, configured to perform a synchronization with at least one device in the NAN cluster, wherein the at least one device comprises an external electronic device, after performing the synchronization, receive, from the external electronic device through the Wi-Fi transceiver, a frame including first data within at least one discovery window (DW) among a plurality of DWs, wherein the first data comprises channel information for second data, and time information for the second data, and based on the channel information and the time information, control the Wi-Fi transceiver to receive the second data at a channel corresponding to the channel information of the received first data during a time duration corresponding to the time information of the received first data.

Abstract: A white organic light emitting device and an organic light emitting display device using the white organic light emitting device stably implement white light in a tandem-type top emission structure through uniform lifespans according to emitted colors of light despite driving of the white organic light emitting device for a long time.

Abstract: A display device includes a display panel having a front surface where images are displayed; a rear-side layer disposed on a rear surface of the display panel, including a plurality of conductive patterns and having first surface unevenness on a front surface thereof; and a support plate disposed between the display panel and the rear-side layer and having a flat surface on a front surface thereof. The support plate includes glass or ceramic.

Abstract: An electronic device includes a display module, and a support plate disposed under the display module and comprising reinforced fibers having long axes arranged in parallel to a direction. The electronic device is divided into a folding area foldable with respect to a folding axis extending in the direction, and a non-folding area adjacent to the folding area.

Abstract: A display device includes a display module and a support plate disposed on the display module and including a plurality of first fibers and a plurality of second fibers disposed on the first fibers and extending to cross the first fibers in a plan view. An opening is defined in the support plate and includes first sides parallel to an extension direction of the first fibers and facing each other and second sides parallel to an extension direction of the second fibers and facing each other.

Abstract: A foldable display device includes a display module including a first non-folding portion, a second non-folding portion, and a first folding portion between the first non-folding portion and the second non-folding portion, a first support member on a lower surface of the display module, the first support member including a first support portion supporting the first non-folding portion, a second support portion supporting the second non-folding portion, and a first opening pattern overlapping the first folding portion, and including a glass material, and a second support member under the first support member and supporting the display module.

Abstract: When a three-dimensional image of a specific subject is acquired by means of an infrared camera and an external light (for example, external light such as sunlight at the time of outdoor photography) having a relatively large intensity exists, it is difficult to acquire the image. To this end, the present invention proposes an electronic device for reducing a current peak by adaptively changing optical power and an exposure time of an infrared camera according to the intensity of external light.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.

Abstract: An electronic apparatus includes a first adhesive member having a first modulus, a second adhesive member having a second modulus, and a flexible member between, and contacting, the first adhesive member and the second adhesive member, wherein a stress relaxation of the first adhesive member is about 70% or less, and wherein an absolute value of a difference between the first modulus and the second modulus is about 0.01 MPa or less.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.