Abstract: Disclosed are an interfacing method and an apparatus for three-dimensional (3D) sketch. According to an example embodiment, the interfacing method for sketching in a virtual space of three dimensions includes determining a surface including an area in which a first user input is received in the virtual space to be a region of interest, controlling a position of the region of interest in the virtual space based on a second user input on the region of interest, and generating at least one sketch line belonging to the region of interest based on a third user input.

Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

Abstract: A display device includes a display panel having a front surface where images are displayed; a rear-side layer disposed on a rear surface of the display panel, including a plurality of conductive patterns and having first surface unevenness on a front surface thereof; and a support plate disposed between the display panel and the rear-side layer and having a flat surface on a front surface thereof. The support plate includes glass or ceramic.

Abstract: A display device includes a display module and a support plate disposed on the display module and including a plurality of first fibers and a plurality of second fibers disposed on the first fibers and extending to cross the first fibers in a plan view. An opening is defined in the support plate and includes first sides parallel to an extension direction of the first fibers and facing each other and second sides parallel to an extension direction of the second fibers and facing each other.

Abstract: An electronic device includes a display module, and a support plate disposed under the display module and comprising reinforced fibers having long axes arranged in parallel to a direction. The electronic device is divided into a folding area foldable with respect to a folding axis extending in the direction, and a non-folding area adjacent to the folding area.

Abstract: A foldable display device includes a display module including a first non-folding portion, a second non-folding portion, and a first folding portion between the first non-folding portion and the second non-folding portion, a first support member on a lower surface of the display module, the first support member including a first support portion supporting the first non-folding portion, a second support portion supporting the second non-folding portion, and a first opening pattern overlapping the first folding portion, and including a glass material, and a second support member under the first support member and supporting the display module.

Abstract: When a three-dimensional image of a specific subject is acquired by means of an infrared camera and an external light (for example, external light such as sunlight at the time of outdoor photography) having a relatively large intensity exists, it is difficult to acquire the image. To this end, the present invention proposes an electronic device for reducing a current peak by adaptively changing optical power and an exposure time of an infrared camera according to the intensity of external light.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.

Abstract: An electronic apparatus includes a first adhesive member having a first modulus, a second adhesive member having a second modulus, and a flexible member between, and contacting, the first adhesive member and the second adhesive member, wherein a stress relaxation of the first adhesive member is about 70% or less, and wherein an absolute value of a difference between the first modulus and the second modulus is about 0.01 MPa or less.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Abstract: An object control method and an object control device are disclosed. The disclosed object control method: detects a control activation/deactivation command generated by a user; detects, in a state in which the control activation/deactivation command is detected, a user command including a movement variation command and a rotation variation command; determines a user input by the movement variation command and the rotation variation command; and controls an object according to the user input.

Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

Abstract: When a three-dimensional image of a specific subject is acquired by means of an infrared camera and an external light (for example, external light such as sunlight at the time of outdoor photography) having a relatively large intensity exists, it is difficult to acquire the image. To this end, the present invention proposes an electronic device for reducing a current peak by adaptively changing optical power and an exposure time of an infrared camera according to the intensity of external light.