Patents by Inventor Yong Liang

Yong Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250858
    Abstract: Pilot symbols and data symbols of a communication frame for an OTFS transmission system are two-dimensionally arranged along the points of a grid in the delay-Doppler domain. The pilot symbols are surrounded by guard symbols. The number of guard symbols in each direction of the Doppler domain is twice the number of the basis expansion modelling (BEM) basis functions used for modelling the communication channel in a receiver, and twice the maximum time delay in terms of delay bins in each direction of the delay domain. The receiver performs an initial pilot-aided channel estimation using BEM of a first BEM order and using the pilot signals, followed by an initial estimation of data symbols using the initial channel estimation, and iteratively performs data aided channel estimation using BEM of a second BEM order and at least the received data signals, until a termination criterion is met.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 25, 2024
    Inventors: Yujie Liu, Yong Liang Guan, David Gonzalez Gonzalez
  • Patent number: 12047634
    Abstract: Exemplary embodiments are directed to a device and method for displaying an electronic program guide. The device receives electronic program guide data and stores it in memory. The device also receives video content associated with a broadcast channel of a content provider over a network. The device combines the electronic program guide data and the video content, such that the electronic program guide content is overlaid onto the video content in a bullet screen format. The combined electronic program guide data and the video content are sent to a display device.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: July 23, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Yong Liang, Qi Wang, Xue-Wei Zhao, Xiang Shen
  • Patent number: 12037700
    Abstract: A method of forming a film comprises growing, using a deposition system, at least a portion of the film and analyzing, using a RHEED instrument, the at least a portion of the film. Using a computer, data is acquired from the RHEED instrument that is indicative of a stoichiometry of the at least a portion of the film. Using the computer, adjustments to one or more process parameters of the deposition system are calculated to control stoichiometry of the film during subsequent deposition. Using the computer, instructions are transmitted to the deposition system to execute the adjustments of the one or more process parameters. Using the deposition system, the one or more process parameters are adjusted.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: July 16, 2024
    Assignee: PSIQUANTUM, CORP.
    Inventors: Yong Liang, John Elliott Ortmann, Jr., John Berg, Ann Melnichuk
  • Publication number: 20240230690
    Abstract: Disclosed is a detachable modularized test platform. The detachable modularized test platform includes a gantry, a control box and a jig box, where a test area is arranged on the jig box, an air cylinder is arranged on the gantry, a control assembly is mounted in the control box, and a test assembly is mounted in the jig box; during testing, a sample to be tested is placed on the test area, and the upper computer sends an instruction to control the air cylinder to extend a driving rod to move to the sample to be tested; and the upper computer sends the instruction to the control assembly in the control box, to complete testing of the sample, and output and upload test data to a server for saving. The present invention employs a modularized structure, which reduces a size, detection is convenient, and applicability is high.
    Type: Application
    Filed: March 1, 2023
    Publication date: July 11, 2024
    Inventors: Junming LI, Defeng Luo, Youshang Qin, Jianlin Huang, Yong Liang, Chengchun Li
  • Publication number: 20240230713
    Abstract: Disclosed is a test box with circuit boards assembled by means of guide rails. The test box includes a box body, a guide rail assembly, a main circuit board, functional circuit boards and an adapter circuit board are arranged in the box body, the functional circuit boards and the main circuit board are perpendicularly in snap fit with the guide rail assembly and are in plug-in connection to the main circuit board by means of terminals, and the adapter circuit board is installed on the inner side wall of the box body and is in plug-in connection to the functional circuit boards by means of terminals. According to the invention, the circuit boards are installed by means of the guide rails, installation procedures are simplified, assembly efficiency is improved, assembly difficulty is reduced, and a space utilization rate is improved.
    Type: Application
    Filed: March 1, 2023
    Publication date: July 11, 2024
    Inventors: Junming LI, Yong LIANG, Youshang QIN, Jianlin HUANG, Defeng LUO, Chengchun LI
  • Patent number: 12018002
    Abstract: Chemical entities that are kinase inhibitors, pharmaceutical compositions and methods of treatment of cancer are described.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: June 25, 2024
    Assignee: NEUPHARMA, INC
    Inventors: Xiangping Qian, Yong-Liang Zhu
  • Publication number: 20240201719
    Abstract: A device includes a voltage regulator circuit configured to pull up a voltage at an output terminal to equal to half of a supply voltage; multiple first transistors coupled between the output terminal and a voltage terminal providing the supply voltage; and a control circuit configured to pull down gate voltages of the first transistors from the supply voltage to a voltage level between the supply voltage and a ground voltage at a first time. The first transistors are configured to pull up the voltage at the output terminal to the supply voltage at a second time.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Yong-Liang JIN, Ya-Qi MA, Wei LI, Di FAN
  • Publication number: 20240197752
    Abstract: Chemical entities that are kinase inhibitors, pharmaceutical compositions and methods of treatment of cancer are described.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 20, 2024
    Inventors: Xiangping QIAN, Yong-Liang ZHU
  • Publication number: 20240201525
    Abstract: A system includes a classical computing system and one or more quantum computing chips coupled to the classical computing system. The one or more quantum computing chips includes one or more electro-optic devices. Each electro-optic device includes a substrate, a waveguide disposed on top of the substrate, and a layer stack disposed on top of the waveguide and including a plurality of electro-optic material layers interleaved with a plurality of interlayers. Each electro-optic device further comprising a waveguide core disposed on top of a portion of the layer stack. The plurality of interlayers are characterized by a first lattice structure and the plurality of electro-optic material layers are under tensile stress and are characterized by a second lattice structure and crystallographic phase.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 20, 2024
    Applicant: Psiquantum, Corp.
    Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240154049
    Abstract: A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer comprises selenium, wherein an atomic concentration of selenium varies across a thickness of the absorber layer. The photovoltaic device is substantially free of a cadmium sulfide layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: First Solar, Inc.
    Inventors: Holly Ann Blaydes, Kristian William Andreini, William Hullinger Huber, Eugene Thomas Hinners, Joseph John Shiang, Yong Liang, Jongwoo Choi
  • Publication number: 20240133906
    Abstract: Disclosed is a detachable modularized test platform. The detachable modularized test platform includes a gantry, a control box and a jig box, where a test area is arranged on the jig box, an air cylinder is arranged on the gantry, a control assembly is mounted in the control box, and a test assembly is mounted in the jig box; during testing, a sample to be tested is placed on the test area, and the upper computer sends an instruction to control the air cylinder to extend a driving rod to move to the sample to be tested; and the upper computer sends the instruction to the control assembly in the control box, to complete testing of the sample, and output and upload test data to a server for saving. The present invention employs a modularized structure, which reduces a size, detection is convenient, and applicability is high.
    Type: Application
    Filed: March 1, 2023
    Publication date: April 25, 2024
    Inventors: Junming LI, Defeng Luo, Youshang Qin, Jianlin Huang, Yong Liang, Chengchun Li
  • Publication number: 20240133920
    Abstract: Disclosed is a test box with circuit boards assembled by means of guide rails. The test box includes a box body, a guide rail assembly, a main circuit board, functional circuit boards and an adapter circuit board are arranged in the box body, the functional circuit boards and the main circuit board are perpendicularly in snap fit with the guide rail assembly and are in plug-in connection to the main circuit board by means of terminals, and the adapter circuit board is installed on the inner side wall of the box body and is in plug-in connection to the functional circuit boards by means of terminals. According to the invention, the circuit boards are installed by means of the guide rails, installation procedures are simplified, assembly efficiency is improved, assembly difficulty is reduced, and a space utilization rate is improved.
    Type: Application
    Filed: March 1, 2023
    Publication date: April 25, 2024
    Inventors: Junming LI, Yong LIANG, Youshang QIN, Jianlin HUANG, Defeng LUO, Chengchun LI
  • Patent number: 11947372
    Abstract: A device includes a voltage regulator circuit configured to pull up a voltage at an output terminal to equal to half of a supply voltage; multiple first transistors coupled between the output terminal and a voltage terminal providing the supply voltage; and a control circuit configured to pull down gate voltages of the first transistors from the supply voltage to a voltage level between the supply voltage and a ground voltage at a first time. The first transistors are configured to pull up the voltage at the output terminal to the supply voltage at a second time.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: April 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Yong-Liang Jin, Ya-Qi Ma, Wei Li, Di Fan
  • Patent number: 11943081
    Abstract: There is provided a method of receiving a transmitted signal over a time-varying channel. The method includes: obtaining a received symbol signal in frequency domain based on the transmitted signal; performing a first channel estimation based on the received symbol signal to obtain a plurality of first estimated BEM coefficients; performing a first equalization based on the received symbol signal and the plurality of first estimated BEM coefficients to obtain a plurality of first detected source symbols; and performing one or more rounds of a second channel estimation and a second equalization.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: March 26, 2024
    Assignees: Nanyang Technological University, Southwest Jiaotong University
    Inventors: Xiaobei Liu, Kushal Anand, Yong Liang Guan, Pingzhi Fan
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240078488
    Abstract: Aspects concern a method for controlling vehicles to perform transport tasks comprising supplying information about vehicles and information about transport tasks to a graph neural network by associating each vehicle with a vehicle graph node and each transport task with a transport task graph node, processing the vehicle and the transport graph by the neural network, wherein the neural network determines a feature for each graph node, determining, for each pair of a transport graph node and vehicle graph node, a weight representing a similarity between the features determined for the transport graph node and the vehicle graph node, selecting an assignment between the transport graph nodes and the vehicle graph nodes from a set of possible assignments, wherein the selected assignment maximizes the sum of the weights of the pairs and controlling each vehicle according to the selected assignment.
    Type: Application
    Filed: May 12, 2022
    Publication date: March 7, 2024
    Inventors: Yong Liang GOH, Wee Sun LEE, Xiang Hui Nicholas LIM
  • Publication number: 20240063146
    Abstract: A wafer includes a silicon layer, a first dielectric layer on the silicon layer, and a ferroelectric layer on the first dielectric layer. The ferroelectric layer defines one or more gaps between portions of the ferroelectric layer. The wafer also includes a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: Psiquantum, Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
  • Publication number: 20240055546
    Abstract: Embodiments of a photovoltaic device are provided herein. The photovoltaic device can include a layer stack and an absorber layer disposed on the layer stack. The absorber layer can include a first region and a second region. Each of the first region of the absorber layer and the second region of the absorber layer can include a compound comprising cadmium, selenium, and tellurium. An atomic concentration of selenium can vary across the absorber layer. The first region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. The second region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. A ratio of an average atomic concentration of selenium in the first region of the absorber layer to an average atomic concentration of selenium in the second region of the absorber layer can be greater than 10.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 15, 2024
    Applicant: First Solar, Inc.
    Inventors: Kristian William Andreini, Holly Ann Blaydes, Jongwoo Choi, Adam Fraser Halverson, Eugene Thomas Hinners, William Hullinger Huber, Yong Liang, Joseph John Shiang
  • Patent number: D1035607
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: July 16, 2024
    Inventor: Yong Liang