Patents by Inventor Yong Liu

Yong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052900
    Abstract: Systems and techniques relating to wireless communications are described. A described technique includes monitoring a group of wireless channels that are useable by at least a first wireless communication device for wireless communications, receiving one or more beacon signals from one or more second wireless communication devices, identifying, within the group of wireless channels, one or more primary channels on which the one or more beacon signals are received, estimating a traffic load for the one or more identified primary channels, determining, based on the estimated traffic load, whether to use as a primary channel for the first wireless communication device, a channel of the one or more identified primary channels or a channel of the group of wireless channels that is separate from the one or more identified primary channels; and selecting the primary channel for the first wireless communication device based on a result of the determining.
    Type: Application
    Filed: August 26, 2011
    Publication date: March 1, 2012
    Inventors: Yong Liu, Harish Ramamurthy
  • Patent number: 8120169
    Abstract: A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the spreader in the MLP. The connecting projection is attached to a lead of the leadframe so that heat gathered by the cap can be transferred through the connecting projection to the lead and to a printed circuit board to which the lead is connected. In embodiments, the heat spreader includes a central heat collector projection from the cap toward the die, preferably in the form of a solid cylinder, that enhances heat collection and transfer to the cap. The cap can include fins projecting from its top surface to facilitate radiant and convection cooling.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 21, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Zhongfa Yuan
  • Patent number: 8119457
    Abstract: A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: February 21, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan A. Noquil, Yong Liu, Jocel Gomez
  • Publication number: 20120038584
    Abstract: A touch panel for determining real coordinates of multiple touch points is provided. The touch panel for determining real coordinates of multiple touch points comprises a sensing path layer having a plurality of first paths and a plurality of second paths for detecting the raw coordinates of said multiple touch points, and an Eliminating Path Layer having a plurality of third paths for eliminating ghost coordinates of said multiple touch points from said raw coordinates to output said real coordinates of said multiple touch points. The method of determining real coordinates of multiple touch points on the touch panel is also provided.
    Type: Application
    Filed: December 6, 2010
    Publication date: February 16, 2012
    Inventor: YONG LIU
  • Publication number: 20120038429
    Abstract: An oscillator circuit includes a field effect transistor (FET), the FET comprising a channel, source, drain, and gate, wherein at least the channel comprises graphene; an LC component connected to the FET, the LC component comprising at least one inductor and at least one capacitor; and a feedback loop connecting the FET source to the FET drain via the LC component.
    Type: Application
    Filed: August 13, 2010
    Publication date: February 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wilfried E. Haensch, Yong Liu, Zihong Liu
  • Patent number: 8115260
    Abstract: This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: February 14, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dan Kinzer, Yong Liu, Stephen Martin
  • Patent number: 8106406
    Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: January 31, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Zhongfa Yuan
  • Patent number: 8102029
    Abstract: A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: January 24, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Qi Wang
  • Publication number: 20120012993
    Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Inventors: Yong Liu, Zhongfa Yuan
  • Publication number: 20120005304
    Abstract: A method and apparatus are described including receiving content from a base station, storing the received content, receiving a second message from a first member of a network, determining a highest expected layer, a lowest layer received by the first member of the network requesting help, a highest layer that needs to be multicast to the first member of the network, and a lowest layer that needs to be multicast to the first member of the network, retrieving the stored content responsive to the message and multicasting the retrieved content to the first member of the network responsive to the determining act.
    Type: Application
    Filed: March 25, 2009
    Publication date: January 5, 2012
    Applicant: THOMSON LICENSING
    Inventors: Yang Guo, Sha Hua, Hang Liu, Yong Liu, Shivendra Panwar
  • Publication number: 20120001313
    Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.
    Type: Application
    Filed: September 8, 2011
    Publication date: January 5, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Margie T. Rios, Hua Yang, Yumin Liu, Tiburcio A. Maldo
  • Publication number: 20120001322
    Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 5, 2012
    Inventors: Yong Liu, Luke England
  • Patent number: 8088645
    Abstract: A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 3, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Yumin Liu, Hua Yang, Tiburcio A. Maldo, Margie T. Rios
  • Patent number: 8082525
    Abstract: Embodiments of a method for determining a mask pattern to be used on a photo-mask in a lithography process are described. This method may be performed by a computer system. During operation, this computer system receives at least a portion of a first mask pattern including first regions that violate pre-determined rules associated with the photo-mask. Next, the computer system determines a second mask pattern based on at least the portion of the first mask pattern, where the second mask pattern includes second regions that are estimated to comply with the pre-determined rules. Note that the second regions correspond to the first regions, and the second mask pattern is determined using a different technique than that used to determine the first mask pattern.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: December 20, 2011
    Assignee: Luminescent Technologies, Inc.
    Inventors: Yong Liu, John F. McCarty, Kelly Gordon Russell, Linyong Pang
  • Publication number: 20110305288
    Abstract: In a method implemented in a communication device an available bandwidth for transmitting one or more data frames is determined, wherein the available bandwidth corresponds to a first composite communication channel comprising a plurality of communication channels. A control frame to indicate a request to transmit via the first composite communication channel is generated, wherein the control frame includes a header, and wherein a portion of the header includes information indicating the bandwidth of the first composite channel. The control frame is transmitted via the first composite communication channel, wherein at least the portion of the header is duplicated in a plurality of bandwidth portions of the first composite communication channel.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 15, 2011
    Inventors: Yong Liu, Harish Ramamurthy, Raja Banerjea
  • Publication number: 20110305156
    Abstract: In a method implemented in a first communication device, a control frame having a bandwidth is generated. The control frame is transmitted via a first composite communication channel, wherein the first composite communication channel comprises a plurality of communication channels. A bandwidth of a response frame, received from a second communication device in response to transmitting the control frame, is determined. A second composite communication channel based on the bandwidth of the response frame is determined, wherein the second composite communication channel comprises at least one communication channel from the plurality of communication channels. One or more data frames are transmitted to the second communication device via the second composite communication channel.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 15, 2011
    Inventors: Yong Liu, Harish Ramamurthy, Raja Banerjea
  • Patent number: 8072962
    Abstract: A method of detecting and solving a network ID conflict is provided. The method of detecting and solving a network ID conflict includes generating and transmitting a personal area network identifier (PAN ID) report command frame that includes an extended PAN ID, and receiving a PAN ID update command frame in response to the transmitted PAN ID report command frame. According to the method, the PAN ID report command and the PAN ID update command are generated and provided by providing an extended PAN ID (EPID), and thus a network ID conflict can be detected and a new PAN ID is provided to solve the network ID conflict.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: December 6, 2011
    Assignees: Samsung Electronics Co., Ltd., City University of New York
    Inventors: Myung-jong Lee, Yong Liu
  • Publication number: 20110287789
    Abstract: The present invention aims to provide a technical solution for recognizing a target device from a plurality of devices as follows: sending a first and second wireless signal to a plurality of devices and determining the target device according to the signal strength differences between the first and second signal strengths. By using the technical solutions of the present invention, the “near-far-effect” caused by a single antenna can be overcome, and different offsets in the measured received signal strengths caused by the diversity of the receiving antennas can also be eliminated, and thus the accuracy of recognition is improved efficiently.
    Type: Application
    Filed: November 26, 2009
    Publication date: November 24, 2011
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Daiqin Yang, Yong Liu, Lei Feng, Zhigang Chen
  • Patent number: 8063474
    Abstract: A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Qiuxiao Qian
  • Patent number: 8063472
    Abstract: Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: November 22, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, William Newberry, Margie T. Rios, Qiuxiao Qian