Patents by Inventor Yong Liu

Yong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7589338
    Abstract: An optocoupler package is disclosed. The package includes a substrate comprising a substrate surface, a first device, and a clip structure attached to the first device. The clip structure and the first device are mounted on the substrate, and the first device is oriented at an angle with respect to the substrate surface. A second device is mounted on the substrate, where the first device is capable of communicating with the second device.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: September 15, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Zhengyu Zhu, Zhongfa Yuan
  • Publication number: 20090221217
    Abstract: The present invention generally relates to an edge deletion module positioned within an automated solar cell fabrication line. The edge deletion module may include a grinding wheel device for removing material from edge regions of a solar cell device and cleaning the edge regions of the solar cell device after removing the material. The edge deletion module may also include an abrasive element, a portion of which is ground as it is periodically, laterally advanced toward the grinding wheel device. A controller is provided for controlling the operation and function of various facets of the module.
    Type: Application
    Filed: January 23, 2009
    Publication date: September 3, 2009
    Applicant: APPLIED MATERIALS, INC.
    Inventors: DHRUV GAJARIA, Zhiyong Li, Gopalakrishna B. Prabhu, Yacov Elgar, John Visitacion, Yong Liu, Jeffrey S. Sullivan, Salvador Umotoy, Tai T. Ngo, Michael Marriott, Peter Crundwell, Vinay Shah, Ho Gene Choi, Dennis C. Pierce
  • Patent number: 7583592
    Abstract: A route recovery method in a wireless network of a tree topology, in which a second node, which is a lower node of a first node and is disconnected from the first node, recovers the route in the network. The route recovery method includes the second node broadcasting a local repair request (LREQ) packet, each node receiving the LREQ packet sending a local repair reply (LREP) packet to the second node to act as a relay node for the route recovery, the second node selecting the relay node from among the nodes sending the LREP packet, and sending a local repair confirm (LCON) packet from the second node to the relay node, and establishing the route between the second node and the first node by the relay node sending a local repair inform (LINF) packet to the first node.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hun Park, Yong Liu, Myung-jong Lee, Xu-hui Hu, Tae-kyung Kwon
  • Publication number: 20090212403
    Abstract: A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the spreader in the MLP. The connecting projection is attached to a lead of the leadframe so that heat gathered by the cap can be transferred through the connecting projection to the lead and to a printed circuit board to which the lead is connected. In embodiments, the heat spreader includes a central heat collector projection from the cap toward the die, preferably in the form of a solid cylinder, that enhances heat collection and transfer to the cap. The cap can include fins projecting from its top surface to facilitate radiant and convection cooling.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Yong Liu, Zhongfa Yuan
  • Publication number: 20090212405
    Abstract: A stacked die molded leadless package (MLP) stacks two dice and uses leads formed integrally with top and central clips and a leadframe to avoid wire bonding. The central clip leads are source and gate leads leading to source and gate portions of the central clip common to source and gate regions of both dice. The top clip and leadframe are thus connected to the drain regions of the upper and lower dice, the leads of the top clip being drain leads connected to the leadframe leads. The central clip and leadframe leads provide source, gate, and drain terminals in the finished MLP. A method of making the MLP includes flip-chip assembly of the clips, dice, and leadframes in pairs or greater simultaneous quantities. Spacers can be employed between connected components to ensure proper alignment and distribution of bonding material.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Yong Liu, Zhongfa Yuan, Erwin lan Almagro
  • Patent number: 7575170
    Abstract: A method of illuminating objects using adaptively controlled mixing of spectral illumination energy to form and detect digital images of objects at POS environments with sufficiently high image contrast and quality. The method comprises providing, at a POS environment, a digital image capture and processing system having a system housing with an imaging window, and a coplanar illumination and imaging station disposed within said system housing, for projecting a coplanar illumination and imaging plane through the imaging window into an imaging volume during object illumination and imaging operations. As the object is moved through the imaging volume, its motion is automatically detected, and signals indicative of said detected object are generated. In response to the generated signals, a first field of visible illumination is produced from an array of visible laser diodes (VLDs), simultaneously with a second field of invisible illumination from a array of infrared (IR) laser diodes (LDs).
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 18, 2009
    Assignee: Metrologic Instruments, Inc.
    Inventors: C. Harry Knowles, Xiaoxun Zhu, Timothy Good, Tao Xian, Anatoly Kotlarsky, Michael Veksland, Mark Hernandez, John Gardner, Steven Essinger, Patrick Giordano, Sean Kearney, Mark Schmidt, John Furlong, Nicholas Ciarlante, Yong Liu, Jie Ren, Xi Tao, JiBin Liu, Ming Zhuo, Duane Ellis
  • Publication number: 20090200657
    Abstract: A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventors: Yong Liu, Yumin Liu, Hua Yang, Tiburcio A. Maldo, Margie T. Rios
  • Patent number: 7571858
    Abstract: A POS-based digital image capturing and processing system for illuminating objects using automatic object detection and spectral-mixing illumination technique. The system comprises a coplanar illumination and imaging station for projecting at least one coplanar illumination and imaging plane into an imaging volume during object illumination and imaging operations. The coplanar illumination and imaging station includes an illumination subsystem for producing a first field of visible illumination from an array of visible VLDs, and producing a second field of invisible illumination from an array of infrared (IR) laser diodes (IR-LDs). Wherein the first and second fields of illumination spatially overlap and intermix with each other and are substantially coplanar with the FOV of the linear image sensing array.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 11, 2009
    Assignee: Metrologic INstruemtns, Inc.
    Inventors: C. Harry Knowles, Xiaoxun Zhu, Timothy Good, Tao Xian, Anatoly Kotlarsky, Michael Veksland, Mark Hernandez, John Gardner, Steven Essinger, Patrick Giordano, Sean Kearney, Mark Schmidt, John A. Furlong, Nicholas Ciarlante, Yong Liu, Jie Ren, Xi Tao, JiBin Liu, Ming Zhuo, Duane Ellis
  • Publication number: 20090194855
    Abstract: A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Inventors: Yong Liu, Hua Yang, Tiburcio A. Maldo
  • Publication number: 20090194857
    Abstract: Disclosed are semiconductor die packages, methods of making them, and systems incorporating them. An exemplary package comprises a first substrate, a second substrate, a semiconductor die disposed between the first and second substrates, and an electrically conductive member disposed between the first and second substrates. The semiconductor die has a conductive region at its first surface that is electrically coupled to a first conductive region of the first substrate, and another conductive region at its second surface that is electrically coupled to a first conductive region of the second substrate. The conductive member is electrically coupled between the first conductive region of the second substrate and a second electrically conductive region of the first substrate. This configuration enables terminals on both surfaces of the semiconductor die to be coupled to the first substrate.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 6, 2009
    Inventors: Yong Liu, Yumin Liu, Hua Yang, Tiburcio A. Maldo
  • Publication number: 20090194887
    Abstract: A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 6, 2009
    Inventors: Yong Liu, Qiuxiao Qian
  • Patent number: 7568625
    Abstract: A method of reading bar code symbols comprising the steps of: (a) projecting an image cropping zone (ICZ) framing pattern within the FOV of an image sensing array during wide-area illumination and image capturing operation; (b) visually aligning an object to be imaged within the ICZ framing pattern; (c) forming and capturing an wide-area image of the entire FOV, which spatially encompasses the ICZ framing pattern aligned about the object to be imaged; (d) using automatic software-based image cropping algorithm to automatically crop the pixels within the spatial boundaries defined by the ICZ framing pattern, from those pixels contained in the entire wide-area image frame captured during step (c); and (e) automatically decode processing the image represented by the cropped image pixels in the ICZ framing pattern so as to read a 1D or 2D bar code symbol graphically represented therein.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 4, 2009
    Assignee: Metpologic Instruments, Inc.
    Inventors: Xiaoxun Zhu, Yong Liu, Ka Man Au, Rui Hou, Hongpeng Yu, Xi Tao, Liang Liu, Wenhua Zhang, Anatoly Kotlarsky, Sankar Ghosh, Michael Schnee, Pasqual Spatafore, Thomas Amundsen, Sung Byun, Mark Schmidt, Garrett Russell, John Bonanno, C. Harry Knowles
  • Publication number: 20090189273
    Abstract: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dice and several parallel leads. The dice are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.
    Type: Application
    Filed: March 17, 2009
    Publication date: July 30, 2009
    Inventors: Yong Liu, Tiburcio A. Maldo, Hua Yang
  • Publication number: 20090189262
    Abstract: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.
    Type: Application
    Filed: January 28, 2008
    Publication date: July 30, 2009
    Inventors: Yong Liu, Tiburcio A. Maldo, Hua Yang
  • Publication number: 20090189266
    Abstract: Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package.
    Type: Application
    Filed: January 28, 2008
    Publication date: July 30, 2009
    Inventors: Yong Liu, William Newberry, Margie T. Rios, Qiuxiao Qian
  • Publication number: 20090184403
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10).
    Type: Application
    Filed: September 14, 2005
    Publication date: July 23, 2009
    Applicant: FREESCALE SEMICONDUCTOR. INC.
    Inventors: Zhi-Jie Wang, Jian-Yong Liu
  • Patent number: 7564786
    Abstract: A method to manage nodes in a ZigBee network. In a ZigBee network including a plurality of nodes, a multicast group is generated including at least two nodes among the plurality of the nodes. A multicast group coordinator (GC) which manages the multicast group is set among the nodes forming the multicast group. The multicast group includes the GC, a multicast group member (GM) requesting to join the multicast group, and/or a multicast router (MR) which links GMs to each other or links the GC and the GC. Accordingly, since the GC manages the multicast group, the load is decreased and the packet data transmission rate is enhanced.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 21, 2009
    Assignees: Samsung Electronics Co., Ltd., City University of New York
    Inventors: Yu-jin Lim, Myung-jong Lee, Xu-hui Hu, Yong Liu, Chun-hui Zhu
  • Patent number: 7564842
    Abstract: The disclosure is a routing method for data in a personal area network. The personal area network includes a plurality of nodes. The method includes receiving a frame at a node, determining whether the node contains a routing table entry for the frame destination, and when the node contains a routing table entry, determining a route for the frame based on a first routing protocol. The method further includes, when the node does not contain a routing table entry for the frame destination, determining whether a route should be discovered for the frame destination, and when a route should not be discovered, determining a route for the frame based on a second routing protocol.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: July 21, 2009
    Assignees: Mitsubishi Electric Research Laboratories, Inc., Samsung Electronics Co. Ltd., Intel Corporation, NXP B.V., Motorola, Inc.
    Inventors: Edgar Herbert Callaway, Jr., Lance Eric Hester, Vernon Anthony Allen, Jasmeet Chhabra, Lakshman Krishnamurthy, Ralph M. Kling, Zafer Sahinoglu, Philip V. Orlik, Phil Jamieson, Phil Rudland, Zachary Smith, Myung J. Lee, Xuhui Hu, Yong Liu, Chunhui Zhu
  • Publication number: 20090174047
    Abstract: Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 9, 2009
    Inventors: Scott Irving, Yong Liu, Qiuxiao Qian
  • Publication number: 20090174048
    Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 9, 2009
    Inventors: Yong Liu, Zhongfa Yuan