Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electric power source arrangement and method of how to use it
    Patent number: 8367258
    Abstract: An electric power source arrangement is described, comprising a fuel cell means (2) having a nominal voltage and a specified voltage-current characteristic, to be connected to a load (1), and comprising a variable DC-DC voltage converter (3), a by-pass branch (11) by-passing the DC-DC voltage converter, a switch (13) alternatively connecting the fuel cell to the DC-DC voltage converter or to the by-pass branch, and a control unit (12) controlling the switch, which control unit (12) comprises a measuring device coupled to the fuel cell means (2) for detecting the operating point thereof and is configured to connect the by-pass branch (11) if the fuel cell means voltage is within a selected range of section (5) of the voltage-current characteristic of the fuel cell means and to disconnect the by-pass branch in the remaining range of sections (4, 6, 7) of said characteristic.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: February 5, 2013
    Assignee: Horizon Fuel Cell Technologies
    Inventors: Zhijun Gu, Ke Jin, Yong Lu
  • Floating source line architecture for non-volatile memory
    Patent number: 8363449
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N?1 memory cells of the plurality via the common floating source line.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 29, 2013
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Hierarchical cross-point array of non-volatile memory
    Patent number: 8363450
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: January 29, 2013
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
  • MRAM DIODE ARRAY AND ACCESS METHOD
    Publication number: 20130003448
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 3, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM
    Publication number: 20120311399
    Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yufei LI, Yong LU, Ying WANG, Hao YANG
  • Mirrored-gate cell for non-volatile memory
    Patent number: 8324607
    Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Seagate Technology LLC
    Inventors: Roger Glenn Rolbiecki, Andrew Carter, Yong Lu
  • Asymmetric write current compensation
    Patent number: 8320169
    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 27, 2012
    Assignee: Seagate Technology LLC
    Inventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
  • Data devices including multiple error correction codes and methods of utilizing
    Patent number: 8296620
    Abstract: A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: October 23, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Data storage using read-mask-write operation
    Patent number: 8289786
    Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Hai Li, Yong Lu
  • Asymmetric write current compensation using gate overdrive for resistive sense memory cells
    Patent number: 8289752
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Non-volatile memory cell with precessional switching
    Patent number: 8289759
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar V. Dimitrov, Wei Tian, Brian S. Lee
  • MRAM diode array and access method
    Patent number: 8289746
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Optical Transceiver Integrated with Optical Time Domain Reflectometer Monitoring
    Publication number: 20120243863
    Abstract: An optical transceiver having an integrated optical time domain reflectometer monitoring unit and methods for using the same are disclosed. The disclosure relates to an optical transceiver comprising an optical device comprising a wavelength division multiplexing system (WDM), a data signal driver, a data signal limiting amplifier, and an optical time domain reflectometer (OTDR) data processing module. Furthermore, the optical transceiver is particularly advantageous in an optical line terminal (OLT) and/or a passive optical network (PON). The integrated OTDR data processing module can protect the optical transceiver, ensure successful monitoring data, simplify network wiring and decrease system and network costs by decreasing the number of OTDR modules and WDM units.
    Type: Application
    Filed: December 2, 2011
    Publication date: September 27, 2012
    Inventors: Fuqiang ZHAO, Yi Yang, Yong Lu
  • Entangled Mate Sequencing
    Publication number: 20120245039
    Abstract: Methods and compositions are provided for performing a set of N DNA sequencing reaction cycles whereby sequence information is obtained for approximately 2*N nucleotide bases.
    Type: Application
    Filed: September 22, 2010
    Publication date: September 27, 2012
    Applicant: President and Fellows of Harvard College
    Inventors: Frederick P. Roth, Joseph C. Mellor, Yong Lu, Mark Chee
  • BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY
    Publication number: 20120230094
    Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Yong Lu, Kang Yong Kim, Young Pil Kim
  • TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT
    Publication number: 20120230093
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Non-volatile memory cell stack with dual resistive elements
    Patent number: 8248836
    Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: August 21, 2012
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, YoungPil Kim, Ming Sun, Chulmin Jung, Venugopalan Vaithyanathan, Nurul Amin, Wei Tian, Yong Lu
  • Non-volatile memory cell with resistive sense element block erase and uni-directional write
    Patent number: 8213259
    Abstract: A non-volatile memory cell and associated method of use. In accordance with some embodiments, the memory cell includes a transistor comprising source and drain regions spanned by a gate region, and a resistive sense element (RSE) connected to the drain region of the transistor. The RSE is programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor. The RSE is programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Seagate Technology LLC
    Inventors: Daniel S. Reed, Yong Lu, Andrew John Carter, Hai Li
  • Current cancellation for non-volatile memory
    Patent number: 8203894
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: June 19, 2012
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
  • Bit line charge accumulation sensing for resistive changing memory
    Patent number: 8203869
    Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 19, 2012
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Kang Yong Kim, Young Pil Kim