Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating source line architecture for non-volatile memory
    Patent number: 8004872
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS
    Publication number: 20110194330
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Application
    Filed: April 18, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • Non-Volatile Memory Cell With Precessional Switching
    Publication number: 20110194337
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tian, Brian Seungwhan Lee
  • Current Cancellation for Non-Volatile Memory
    Publication number: 20110182106
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Application
    Filed: April 6, 2011
    Publication date: July 28, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
  • Transmission gate-based spin-transfer torque memory unit
    Patent number: 7974119
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: July 5, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device
    Publication number: 20110149639
    Abstract: A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew John Carter, Maroun Georges Khoury, Yong Lu, Roger Glenn Rolbiecki
  • Current cancellation for non-volatile memory
    Patent number: 7965565
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 21, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
  • Asymmetric Write Current Compensation
    Publication number: 20110134688
    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
  • VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20110134682
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Variable write and read methods for resistive random access memory
    Patent number: 7952917
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 31, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells
    Publication number: 20110116302
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Application
    Filed: January 27, 2011
    Publication date: May 19, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Resistive sense memory array with partial block update capability
    Patent number: 7944731
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array
    Patent number: 7944729
    Abstract: Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • Non-volatile memory cell with precessional switching
    Patent number: 7936592
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tan, Brian Seungwhan Lee
  • MRAM diode array and access method
    Patent number: 7936580
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Polarity dependent switch for resistive sense memory
    Patent number: 7935619
    Abstract: Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
  • Table-based reference voltage characterization scheme
    Patent number: 7936629
    Abstract: Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Andrew J. Carter, Maroun Khoury, Yong Lu, Yiran Chen
  • Memory array with read reference voltage cells
    Patent number: 7936588
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • Non-volatile memory cell with multiple resistive sense elements sharing a common switching device
    Patent number: 7933136
    Abstract: A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 26, 2011
    Assignee: Seagate Technology LLC
    Inventors: Andrew John Carter, Maroun Georges Khoury, Yong Lu, Roger Glenn Rolbiecki
  • MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS
    Publication number: 20110089509
    Abstract: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 21, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Hongyue Liu, Zheng Gao, Insik Jin, Dimitar V. Dimitrov