Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bidirectional Non-Volatile Memory Array Architecture
    Publication number: 20120147659
    Abstract: Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate structure of each of the switching devices. A plurality of conductive bit lines extend in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells. A control circuit senses a programmed state of a selected memory cell by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level.
    Type: Application
    Filed: February 20, 2012
    Publication date: June 14, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew John Carter, Yong Lu
  • Transmission gate-based spin-transfer torque memory unit
    Patent number: 8199563
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 12, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • nvSRAM having variable magnetic resistors
    Patent number: 8194438
    Abstract: Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yongchul Ahn, Antoine Khoueir, Yong Lu, Hongyue Liu
  • Computer memory device with multiple interfaces
    Patent number: 8194437
    Abstract: Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • Spin-transfer torque memory self-reference read method
    Patent number: 8194444
    Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: June 5, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Yiran Chen, Xiaobin Wang, Zheng Gao, Dimitar V. Dimitrov, Wenzhong Zhu, Yong Lu
  • Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells
    Publication number: 20120120713
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 17, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS
    Publication number: 20120120708
    Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
  • Air-Based Geothermal Cooling System For A Telecom Utility Cabinet
    Publication number: 20120103557
    Abstract: In one embodiment, the disclosure includes an air-based geothermal cooling system for a telecom utility cabinet. The air-based geothermal cooling system includes a plurality of heat exchange tubes configured to extend into an underground environment. The air-based geothermal cooling system also includes an input/output (I/O) manifold coupled to the plurality of heat exchange tubes and providing an airway between the plurality of heat exchange tubes and the telecom utility cabinet.
    Type: Application
    Filed: July 18, 2011
    Publication date: May 3, 2012
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Pedro Fernandez, Shanjiu Chi, Amit Kulkarni, Liqian Zhai, Kelly C. Johnson, Yong Lu, Mahmoud Elkenaney
  • Telecom Utility Cabinet Arranged For Air-Based Geothermal Cooling
    Publication number: 20120103558
    Abstract: In one embodiment, the disclosure includes a telecom utility cabinet including a heat load chamber. The telecom utility cabinet also includes an air introducing duct configured to conduct air from the heat load chamber to a geothermal cooling system. The telecom utility cabinet also includes an air discharging duct configured to conduct air from the geothermal cooling system to the heat load chamber. In another embodiment, the disclosure includes a method for managing temperature in a telecom utility cabinet. The method includes introducing air from a heat load chamber to a geothermal cooling system and discharging air from the geothermal cooling system to the heat load chamber.
    Type: Application
    Filed: July 18, 2011
    Publication date: May 3, 2012
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Pedro Fernandez, Shanjiu Chi, Amit Kulkarni, Liqian Zhai, Kelly C. Johnson, Yong Lu, Mahmoud Elkenaney
  • Air-Based Geothermal Cooling Maintenance System
    Publication number: 20120103560
    Abstract: In one embodiment, a system includes a telecom utility cabinet and an air-based geothermal cooling system for the telecom utility cabinet. The system also includes a leak detector for the air-based geothermal cooling system. In another embodiment, a method includes detecting a leak in an air-based geothermal cooling system. The method also includes activating a liquid pump for the air-based geothermal cooling system in response to the leak detection.
    Type: Application
    Filed: July 18, 2011
    Publication date: May 3, 2012
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Pedro Fernandez, Shanjiu Chi, Amit Kulkarni, Liqian Zhai, Kelly C. Johnson, Yong Lu, Mahmoud Elkenaney
  • Air-Based Geothermal Cooling System Criteria For Telecom Utility Cabinet
    Publication number: 20120103559
    Abstract: In one embodiment, a system includes a telecom utility cabinet and an air-based geothermal cooling system for the telecom utility cabinet. The air-based geothermal cooling system forms an air circulation loop that receives air from the telecom utility cabinet and returns cooled air to the telecom utility cabinet. In another embodiment, an air-based geothermal cooling system for a telecom utility cabinet is provided. The air-based geothermal cooling system comprises a plurality of heat exchange tubes configured to extend into an underground environment. The plurality of heat exchange tubes are part of an air circulation loop configured to receive air from the telecom utility cabinet and to return cooled air to the telecom utility cabinet.
    Type: Application
    Filed: July 18, 2011
    Publication date: May 3, 2012
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Pedro Fernandez, Shanjiu Chi, Amit Kulkarni, Liqian Zhai, Kelly C. Johnson, Yong Lu, Mahmoud Elkenaney
  • Asymmetric Write Current Compensation
    Publication number: 20120087175
    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 12, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
  • Asymmetric write current compensation using gate overdrive for resistive sense memory cells
    Patent number: 8125819
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: February 28, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • High Speed Bi-Directional Transceiver, Circuits and Devices Therefor, and Method(s) of Using the Same
    Publication number: 20120045202
    Abstract: The present disclosure relates to a high-speed and/or power-saving bi-directional transceiver. The transceiver generally includes a (burst) laser driver; an output power monitoring and indicating circuit; control logic (e.g., a microcontroller unit); bi-directional optics; a photodiode bias control circuit; a limiting amplifier; and a receiver optical power monitoring circuit. Optionally, the present transceiver includes a small form factor pluggable (SFP+) connector housing. In addition, the power-saving bi-directional transceiver generally includes a transmitter (TX) energy-saving circuit, a TX burst holding circuit, a receiver (RX) energy-saving circuit, a RX continuous holding circuit and the control logic.
    Type: Application
    Filed: May 11, 2011
    Publication date: February 23, 2012
    Inventors: Xu Jiang, Yi Yang, Yong Lu, Yuan Song
  • Bidirectional non-volatile memory array architecture
    Patent number: 8120941
    Abstract: A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total number of M+N+1 control lines extend adjacent to and are connected with the memory cells to facilitate bi-directional programming of resistive states to each memory cell.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Seagate Technology LLC
    Inventors: Andrew John Carter, Yong Lu
  • THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS
    Publication number: 20120039113
    Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
  • MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY
    Publication number: 20120037875
    Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Roger Glenn Rolbiecki, Andrew Carter, Yong Lu
  • Hierarchical Cross-Point Array of Non-Volatile Memory
    Publication number: 20120039112
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
    Type: Application
    Filed: October 24, 2011
    Publication date: February 16, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
  • POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY
    Publication number: 20120039111
    Abstract: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 16, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
  • Bit Set Modes for a Resistive Sense Memory Cell Array
    Publication number: 20120033482
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Application
    Filed: October 17, 2011
    Publication date: February 9, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman