Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Asymmetric write current compensation
    Patent number: 8107282
    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 31, 2012
    Assignee: Seagate Technology LLC
    Inventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
  • Memory array with read reference voltage cells
    Patent number: 8098513
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • Spin-torque bit cell with unpinned reference layer and unidirectional write current
    Patent number: 8098538
    Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Daniel Seymour Reed, Yong Lu, Song S. Xue, Dimitar V. Dimitrov, Paul E. Anderson
  • Hierarchical cross-point array of non-volatile memory
    Patent number: 8098507
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
  • Data Storage Using Read-Mask-Write Operation
    Publication number: 20120008374
    Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Henry F. Huang, Hai (Helen) Li, Yong Lu
  • Aggregation of product data provided from external sources for presentation on an E-commerce website
    Patent number: 8086496
    Abstract: Aggregation of product data provided from external sources of product data for presentation on an e-commerce website. A set of product data related to a product that is offered for sale in e-commerce is accessed and subjected to an aggregation process. The set of product data is mapped for aggregation with other sets of product data based on an existing mapping or on an absence of an existing mapping. Access is provided to an aggregated set of product data that includes the set of product data that is mapped for aggregation with other sets of product data, for presentation on an e-commerce website.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: December 27, 2011
    Assignee: Microsoft Corporation
    Inventors: Yong Lu, Trevin Chow, Herman John Man, Derek Lynn Jamison, Mark Wong
  • Computer memory device with status register
    Patent number: 8081504
    Abstract: Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: December 20, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Hongyue Liu, Hai Li
  • Floating Source Line Architecture for Non-Volatile Memory
    Publication number: 20110299323
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 8, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Polarity dependent switch for resistive sense memory
    Patent number: 8072014
    Abstract: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: December 6, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
  • Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells
    Publication number: 20110292716
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Three dimensionally stacked non volatile memory units
    Patent number: 8054673
    Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
  • Variable write and read methods for resistive random access memory
    Patent number: 8054675
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Mirrored-gate cell for non-volatile memory
    Patent number: 8053749
    Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Roger Glenn Rolbiecki, Andrew Carter, Yong Lu
  • NAND flash memory with integrated bit line capacitance
    Patent number: 8050092
    Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Harry Hongyue Liu, Brian Lee, Yong Lu, Dadi Setiadi
  • Multi-stage parallel data transfer
    Patent number: 8045412
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Data storage using read-mask-write operation
    Patent number: 8040743
    Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Hai (Helen) Li, Yong Lu
  • Bit set modes for a resistive sense memory cell array
    Patent number: 8040713
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT
    Publication number: 20110228598
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Asymmetric write current compensation using gate overdrive for resistive sense memory cells
    Patent number: 8009458
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current
    Publication number: 20110205788
    Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Daniel Seymour Reed, Yong Lu, Song S. Xue, Dimitar V. Dimitrov, Paul E. Anderson