Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385964
    Abstract: The present application belongs to the field of chiplet technologies and discloses a method, device and storage medium for request processing under mixed cacheline granules. The method is applied to a processor, where a level 2 cache and a level 1 cache of the processor are integrated into a processor chiplet, and a level 3 cache of the processor is integrated into a fabric chiplet. The method includes: acquiring a level 1 cacheline granule of the level 1 cache and a level 3 cacheline granule of the level 3 cache; determining a cache working mode according to the level 1 cacheline granule and the level 3 cacheline granule; and receiving request information and processing the request information based on the cache working mode.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 21, 2024
    Applicants: HEXIN Technologies (Suzhou) Co., Ltd., Shanghai HEXIN Digital Technologies Co., Ltd.
    Inventors: Yangfan LIU, Shi SHI, Pengfei GOU, Yong LU, Yue XU
  • Patent number: 12148654
    Abstract: Embodiments of the present application provide a semiconductor structure and its manufacturing method. The method for manufacturing a semiconductor structure includes: providing a substrate and a dielectric layer located on the substrate, the substrate being provided therein with a conductive structure; etching a certain thickness of the dielectric layer to form a first groove; performing an isotropic etching process on the dielectric layer located at the bottom of the first groove to form a second groove, a maximum width of the second groove being greater than a bottom width of the first groove in a direction parallel with a surface of the substrate; and etching the dielectric layer located at the bottom of the second groove to form a third groove exposing the conductive structure.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 19, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yong Lu, Minghung Hsieh
  • Publication number: 20240379996
    Abstract: An oxide-based solid-state battery cell includes a cathode electrode comprising a cathode current collector. A cathode active layer is arranged adjacent to the cathode current collector and comprising cathode active material that exchanges lithium ions and a solid oxide electrolyte and an in-situ polymerization gel. A separator layer comprises a solid oxide electrolyte, a porous layer, and the in-situ polymerization gel. An anode electrode comprises an anode current collector, a silicon film, and the in-situ polymerization gel.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 14, 2024
    Inventors: Qili SU, Zhe Li, Yong Lu, Haijing Liu
  • Publication number: 20240379997
    Abstract: A solid-state battery cell includes a cathode electrode includes a cathode current collector and a cathode active layer arranged on the cathode current collector and including cathode active material and a solid electrolyte. A separator layer comprises the solid electrolyte. An anode layer comprises an anode current collector and a silicon layer arranged on the anode current collector and including a plurality of concave spherical surfaces.
    Type: Application
    Filed: April 12, 2024
    Publication date: November 14, 2024
    Inventors: Zhe LI, Qili SU, Yong LU, Haijing LIU
  • Patent number: 12114478
    Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 8, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi Wu, Yong Lu, Longyang Chen
  • Patent number: 12100715
    Abstract: Example array substrates are provided. One example array substrate includes an underlying substrate, an antenna and a component layer, where the antenna and the component layer are located on a same side of the underlying substrate, where the component layer and the antenna are disposed at intervals, where the component layer includes a plurality of metal laminates and a plurality of dielectric laminates that are stacked, and where the plurality of metal laminates and the plurality of dielectric laminates are alternately disposed to form a plurality of thin film transistors.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: September 24, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huajun Cao, Guozhong Ma, Yukun Guo, Yong Lu
  • Publication number: 20240282970
    Abstract: An electrode for a lithium-ion battery cell includes a first region having a first thickness and including an active material comprising a first wt % of the first region and a solid electrolyte comprising a second wt % of the first region. A second region has a second thickness and includes the active material comprising a third wt % of the second region and the solid electrolyte comprising a fourth wt % of the second region. The first region and the second region are arranged adjacent to one another. The first wt % is greater than the third wt % and the second wt % is less than the fourth wt %.
    Type: Application
    Filed: June 16, 2023
    Publication date: August 22, 2024
    Inventors: Qili SU, Zhe Li, Yong Lu, Haijing Liu, Dave G. Rich
  • Publication number: 20240283057
    Abstract: A solid-state battery cell includes an anode electrode comprising an anode current collector and an anode coating. A cathode electrode comprises a cathode current collector and a cathode coating, wherein the anode electrode and the cathode electrode exchange lithium ions. A separator layer is arranged between the anode electrode and the cathode electrode. A first capacitor electrode is arranged at least one of between the anode coating and a first side of the separator layer, between the anode coating and the anode current collector, between a second side of the separator layer and the cathode coating, and between the cathode coating and the cathode current collector.
    Type: Application
    Filed: July 27, 2023
    Publication date: August 22, 2024
    Inventors: Yong LU, Zhe Li, Qili SU, Dave G. RICH, Haijing LIU
  • Publication number: 20240283009
    Abstract: A method for preparing an electrolyte layer supported by a dry process electrode layer, the method includes providing a sulfide electrolyte layer; providing a first dry process electrode layer; arranging a first side of the sulfide electrolyte layer adjacent to a first side of the first dry process electrode layer; and calendaring the sulfide electrolyte layer and the first dry process electrode layer to reduce a thickness of the sulfide electrolyte layer to a predetermined thickness in a range from approximately 5 micrometers (?m) to approximately 50 ?m.
    Type: Application
    Filed: July 26, 2023
    Publication date: August 22, 2024
    Inventors: Qili SU, Zhe Li, Meiyuan Wu, Dave G. Rich, Yong Lu, Haijing Liu, Mark W. Verbrugge
  • Publication number: 20240272236
    Abstract: A bipolar battery system includes N battery cells. Each of the N battery cells comprises M cores each comprising a first current collector, cathode active material, a separator, anode active material, and a second current collector, where M is an integer greater than one. The M cores are connected in parallel by connecting the first current collectors of the M cores in each of the N battery cells together and by connecting the second current collectors of the M cores in each of the N battery cells together. N-1 clad plates are arranged between adjacent ones of the N battery cells and the N battery cells are connected in series by the N-1 clad plates. A voltage sensing system connects to the N-1 tabs, a first terminal, and a second terminal and is configured to determine N voltages across the N battery cells, respectively.
    Type: Application
    Filed: July 28, 2023
    Publication date: August 15, 2024
    Inventors: Yong LU, Meiyuan Wu, Zhe LI, Dave G. Rich, Haijing Liu
  • Publication number: 20240274980
    Abstract: A functionalized separator for a battery cell includes a separator layer including a first side and a second side. A functionalized layer is arranged on at least one of the first side and the second side of the separator layer. The functionalized layer comprises a lithium-ion conducting solid electrolyte and a capacitor active material.
    Type: Application
    Filed: August 4, 2023
    Publication date: August 15, 2024
    Inventors: Zhe LI, Meiyuan WU, Qili SU, Dave G. Rich, Yong Lu, Haijing LIU
  • Publication number: 20240274984
    Abstract: A battery cell including an anode electrode layer including an anode active material. A cathode electrode layer comprises cathode active material. A solid electrolyte layer is arranged between the anode electrode layer and the cathode electrode layer. An elastomeric layer is arranged between the anode electrode layer and the solid electrolyte layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: August 15, 2024
    Inventors: Zhe Li, Qili Su, Dave G. Rich, Yong Lu, Haijing Liu
  • Publication number: 20240234811
    Abstract: An electrochemical cell that cycles lithium ions includes a positive electrode that includes a positive electroactive material, a negative electrode that includes a negative electroactive material, and a free-standing separating layer disposed between the positive electrode and the negative electrode. The free-standing separating layer includes a gel membrane that includes a polymer host and a liquid electrolyte and an integrated structural component disposed within the gel membrane. The integrated structural component may be selected from the group consisting of: a plurality of solid-state electrolyte particles, a nonwoven material, and a combination thereof.
    Type: Application
    Filed: April 5, 2023
    Publication date: July 11, 2024
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zhe LI, Qili SU, Meiyuan WU, Yong LU, Haijing LIU
  • Patent number: 11984472
    Abstract: A double-sided capacitor structure and a method for forming the same are provided. The method includes: providing a base including a substrate, capacitor contacts in the substrate, a stacked structure on a surface of the substrate, and capacitor holes penetrating through the stacked structure and exposing the capacitor contacts, and the stacked structure includes sacrificial layers and supporting layers which are alternately stacked in a direction perpendicular to the substrate; forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; filling the capacitor holes with a first conductive material to form a first conductive filling layer; completely removing several of the sacrificial layers and/or the supporting layers to remain at least two of the supporting layers; and forming a second dielectric layer and a third electrode layer that covers a surface of the second dielectric layer.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong Lu
  • Publication number: 20240154104
    Abstract: A battery cell includes an anode electrode comprising a first current collector. Anode active material is arranged on a first surface of the first current collector and is configured to exchange lithium ions. The anode active material comprises silicon. Empty spaces are formed in the anode active material in a predetermined pattern. A solid electrolyte layer is arranged adjacent to the anode electrode. A cathode electrode comprises a second current collector and cathode active material configured to exchange lithium ions and arranged adjacent to the solid electrolyte layer.
    Type: Application
    Filed: August 1, 2023
    Publication date: May 9, 2024
    Inventors: Zhe LI, Xingcheng XIAO, Qili SU, Yong LU, Haijing LIU
  • Publication number: 20240154097
    Abstract: An anode electrode includes a current collector and a first anode layer arranged on the current collector and comprising first anode active material. A first pre-lithiation layer is arranged on the first anode layer. A second anode layer arranged on the first pre-lithiation layer and comprising second anode active material.
    Type: Application
    Filed: March 30, 2023
    Publication date: May 9, 2024
    Inventors: Qili Su, Zhe Li, Yong Lu, Haijing Liu
  • Publication number: 20240154126
    Abstract: A bipolar battery cell includes a bipolar electrode including a bipolar current collector and a cathode electrode arranged on one side of the bipolar current collector. The cathode electrode includes cathode active material for exchanging lithium ions, a first solid electrolyte, and first polytetrafluoroethylene (PTFE) fibrils. An anode electrode is arranged on an opposite side of the bipolar current collector, wherein the anode electrode includes anode active material for exchanging lithium ions, a second solid electrolyte, and second PTFE fibrils.
    Type: Application
    Filed: July 31, 2023
    Publication date: May 9, 2024
    Inventors: Yong LU, Zhe Li, Qili Su, Haijing Liu
  • Publication number: 20240154095
    Abstract: An electrochemical cell includes a first electrode that includes a first current collector and a first electroactive material layer disposed on or near the first current collector, a second electrode that includes a second current collector and a second electroactive material layer disposed on or near the second current collector, and a separating layer disposed between the first electroactive material layer and the second electroactive material layer. The second electroactive material layer includes a plurality of hierarchical silicon columns, each of the hierarchical silicon columns has a longest dimension perpendicular to a major axis of the second current collector. The second electroactive material layer also includes a carbonaceous network that at least partially fills interstices defined between hierarchical silicon columns of the plurality of hierarchical silicon columns. The carbonaceous network includes linked carbon atoms that define a plurality of pores.
    Type: Application
    Filed: March 28, 2023
    Publication date: May 9, 2024
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zhe LI, Xingcheng XIAO, Qili SU, Yong LU
  • Patent number: 11980020
    Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong Lu
  • Patent number: 11972557
    Abstract: Provided are a vibration object monitoring method and apparatus, a computer device, and a storage medium. The method includes: in response to detecting that a vibration object exists in a monitoring video picture for a target monitoring region, a vibration object region in the monitoring video picture is determined, where the vibration object region is a region where the vibration object is located in the monitoring video picture; displacement information of a key point of the vibration object in the vibration object region is recorded; vibration information of the vibration object in the monitoring video picture is determined based on the displacement information; and a vibration object monitoring result for the target monitoring region is generated according to the vibration information. The abnormal vibration monitoring can be performed on the vibration object in the target monitoring region in time according to this method.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 30, 2024
    Assignee: CSG POWER GENERATION CO., LTD.
    Inventors: Yumin Peng, Zhiqiang Wang, Hao Zhang, Hengjun Chen, Xun Hu, Tuixiang Feng, Liqun Sun, Man Chen, Yong Lu, Tao Liu, Kai Lin, Yulin Han