Abstract: Disclosed is a technique for switching from a master node to a secondary node in a communication system. A method of a first communication node may comprise: adding the first communication node as a primary secondary cell (PSCell) to a second communication node through dual connectivity (DC); generating a first user plane path for smart dynamic switching (SDS) and a first instance for supporting the first user plane path according to a request from the second communication node; transmitting information on the first user plane path and the first instance to a terminal; receiving user data based on the first user plane path from the terminal as the first instance; and transmitting the user data to a core network using the first user plane path.

Abstract: A negative electrode active material for a lithium secondary battery which includes: silicon particles; and a coating layer surrounding respective silicon particles, wherein the silicon particles have a full width at half maximum (FWHM) of peak ranging from 2 to 10 in the particle diameter distribution having an average particle diameter (D50) of 1 ?m to 30 ?m, and the coating layer includes at least one selected from the group consisting of carbon and a polymer. A negative electrode and lithium secondary battery including the negative electrode active material are also disclosed.

Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.

Abstract: The present application relates to a peptide having protective activity against cell damage caused by particulate matter, and to uses for the peptide.

Abstract: A light-emitting element ink, a display device, and a method of fabricating the display device are provided. The light-emitting element ink includes a light-emitting element solvent, light-emitting elements dispersed in the light-emitting element solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film that surrounds parts of outer surfaces of the semiconductor layers, and a surfactant dispersed in the light-emitting element solvent, the surfactant including a fluorine-based and/or a silicon-based surfactant.

Abstract: A silicon-carbon complex comprising carbon-based particles and silicon-based particles, wherein the silicon-based particles are dispersed and positioned on surfaces of the carbon-based particles, the carbon-based particles have a specific surface area of 0.4 m2/g to 1.5 m2/g, and the silicon-based particles are doped with one or more elements selected from the group consisting of Mg, Li, Ca, and Al, and a negative electrode active material for lithium secondary battery comprising the same.

Abstract: A method of manufacturing a multilayer electronic component includes forming a stack by stacking a plurality of ceramic green sheets on which conductive patterns are disposed on a support film, cutting the stack in a second direction, perpendicular to a first direction which is a stacking direction of the plurality of ceramic green sheets, cutting the stack in a third direction, perpendicular to the first and second directions, to obtain a plurality of unit chips, separating the unit chip from the support film, arranging the unit chip such that one of side surfaces of the unit chip is in contact with an adhesive tape, and attaching another one of the side surfaces to a ceramic green sheet for a side margin portion, and forming a side margin portion on the another one of side surfaces.

Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A method for mobilizing leukemia cells which are ?4 integrin positive to the peripheral blood of a human subject, the method comprising administering to the human subject an effective amount of an antisense compound to ?4 integrin. The cells may be mobilized from bone marrow. The antisense compound is: 5?-MeCMeUG AGT MeCTG TTT MeUMeCMeC AMeUMeU MeCMeU-3? wherein, (a) each of the 19 internucleotide linkages of the oligonucleotide is an O,O-linked phosphorothioate diester; (b) the nucleotides at the positions 1 to 3 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; (c) the nucleotides at the positions 4 to 12 from the 5? end are 2?-deoxyribonucleosides; (d) the nucleotides at the positions 13 to 20 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; and (e) all cytosines are 5-methylcytosines (MeC), or a pharmaceutically acceptable salt thereof.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates a first error scrub control signal and a second error scrub control signal according to a logic level combination of an error code including information on the error occurrence number of times. The second semiconductor device performs an error scrub operation of a memory area on a first cycle time in response to the first error scrub control signal during a refresh operation and performs the error scrub operation of the memory area on a second cycle time in response to the second error scrub control signal during the refresh operation.

Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.

Abstract: A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.

Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.