Abstract: A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y

Abstract: A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.

Abstract: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal.

Abstract: An apparatus for controlling on-die termination of a semiconductor memory includes a detector that generates an ODT control signal for inactivating an on-die termination operation in one of a data read period and a data write period in response to a command signal for testing the on-die termination operation, and a controller that inactivates the on-die termination operation in response to the ODT control signal.

Abstract: Disclosed are a power supply circuit for an oscillator of a semiconductor memory device and a voltage pumping device using the same. In the power supply circuit, a voltage divider divides a voltage between an external power supply and ground. A driver is controlled by a signal of the voltage divided by the voltage divider. The driver supplies an internal power supply voltage. A capacitor is coupled between the driver and the ground. As the level of an external power supply voltage is increased, a relatively low voltage is supplied to the oscillator to increase a cycle length of an output pulse signal of the oscillator. Therefore, an excessive increase in the internal power supply voltage due to over-pumping can be avoided and noise occurrence and electric current consumption can be reduced.

Abstract: A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

Abstract: A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using an decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module.

Abstract: A semiconductor memory device is capable of adjusting effective data period of data. The semiconductor memory device includes a buffering unit for buffering input data, a window adjusting unit, and a transmitting unit. The window adjusting unit is for adjusting a window of the buffered data outputted from the buffering unit in response to plural metal option. The window adjusting unit includes a first driving unit for driving an output node in response to the output signal from the buffering unit and a second driving unit for additionally driving the output node in response to the output signal from the buffering unit. Meanwhile, the transmitting unit delivers output of the window adjusting unit into a core block.