Abstract: A semiconductor memory device is capable of adjusting effective data period of data. The semiconductor memory device includes a buffering unit for buffering input data, a window adjusting unit, and a transmitting unit. The window adjusting unit is for adjusting a window of the buffered data outputted from the buffering unit in response to plural metal option. The window adjusting unit includes a first driving unit for driving an output node in response to the output signal from the buffering unit and a second driving unit for additionally driving the output node in response to the output signal from the buffering unit. Meanwhile, the transmitting unit delivers output of the window adjusting unit into a core block.

Abstract: A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the global signal based on the plurality of driving control signals in order to drive the global signal to the plurality of banks.

Abstract: A data input device of a semiconductor memory device can reduce unnecessary current consumption occurring according to a setting of a bandwidth. The data input device includes: a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwidth to output an internal bandwidth signal; a synchronization control part for generating synchronization signals and restrict-synchronization signals in synchronization with a data strobe signal, an activation of the restrict-synchronization signals being restricted through the internal bandwidth signal; a first data input part for aligning the data in response to the synchronization signals; and a second data input part for aligning the data in response to the restrict-synchronization signal and the internal bandwidth signal.

Abstract: An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.

Abstract: An apparatus for controlling on-die termination of a semiconductor memory includes a detector that generates an ODT control signal for inactivating an on-die termination operation in one of a data read period and a data write period in response to a command signal for testing the on-die termination operation, and a controller that inactivates the on-die termination operation in response to the ODT control signal.

Abstract: The disclosure is a device for applying a test voltage from the external of a memory device in a burn-in test mode. An internal voltage generator for a burn-in test is comprised of pad means receiving an external voltage, switching means turned on in the burn-in test mode, and an internal voltage generating means. An external voltage applied to the pad means during the burn-in test mode is transferred to the internal voltage generating means by way of the switching means.

Abstract: An on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an output node for outputting an output signal and assigned with different resistance values; and a control signal generation block for generating a plurality of pull up and pull down control signals for turning on/off the plurality of output driver units in response to output signals of the decoding unit.

Abstract: A data input device of a semiconductor memory device can reduce unnecessary current consumption occurring according to a setting of a bandwidth. The data input device includes: a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwidth to output an internal bandwidth signal; a synchronization control part for generating synchronization signals and restrict-synchronization signals in synchronization with a data strobe signal, an activation of the restrict-synchronization signals being restricted through the internal bandwidth signal; a first data input part for aligning the data in response to the synchronization signals; and a second data input part for aligning the data in response to the restrict-synchronization signal and the internal bandwidth signal.

Abstract: A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the global signal based on the plurality of driving control signals in order to drive the global signal to the plurality of banks.

Abstract: A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using an decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module.

Abstract: An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.

Abstract: A semiconductor memory device is capable of adjusting effective data period of data. The semiconductor memory device includes a buffering unit for buffering input data, a window adjusting unit, and a transmitting unit. The window adjusting unit is for adjusting a window of the buffered data outputted from the buffering unit in response to plural metal option. The window adjusting unit includes a first driving unit for driving an output node in response to the output signal from the buffering unit and a second driving unit for additionally driving the output node in response to the output signal from the buffering unit. Meanwhile, the transmitting unit delivers output of the window adjusting unit into a core block.

Abstract: An on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an output node for outputting an output signal and assigned with different resistance values; and a control signal generation block for generating a plurality of pull up and pull down control signals for turning on/off the plurality of output driver units in response to output signals of the decoding unit.

Abstract: Provided is directed to a negative word line driver, including: a block select address generation unit for generating first and second block select addresses having a block information according to an active signal; a row decoder controller for generating a control signal to disable a word line; a main word line driver for accessing a main word line by being driven in response to a signal coding the first block select address and the control signal; and a phi X driver for accessing a sub word line by being driven in response to a signal coding the second block select address and the control signal wloff.

Abstract: There is provided a semiconductor memory device which is capable of reducing a current consumption in an active mode. The semiconductor memory device includes an internal voltage supply block and an internal voltage control block. The internal voltage supplying block is enabled in response to an internal voltage driving enable signal and generates an internal voltage used in an internal operation of the semiconductor memory device. The internal voltage control block activates the internal voltage driving enable signal during a predetermined period after the semiconductor memory device enters an active operation period and during a period corresponding to read/write operations.

Abstract: There is provided a semiconductor memory device which is capable of reducing a current consumption in an active mode. The semiconductor memory device includes an internal voltage supply block and an internal voltage control block. The internal voltage supplying block is enabled in response to an internal voltage driving enable signal and generates an internal voltage used in an internal operation of the semiconductor memory device. The internal voltage control block activates the internal voltage driving enable signal during a predetermined period after the semiconductor memory device enters an active operation period and during a period corresponding to read/write operations.