Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates a first error scrub control signal and a second error scrub control signal according to a logic level combination of an error code including information on the error occurrence number of times. The second semiconductor device performs an error scrub operation of a memory area on a first cycle time in response to the first error scrub control signal during a refresh operation and performs the error scrub operation of the memory area on a second cycle time in response to the second error scrub control signal during the refresh operation.

Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

Abstract: A method for mobilizing leukemia cells which are ?4 integrin positive to the peripheral blood of a human subject, the method comprising administering to the human subject an effective amount of an antisense compound to ?4 integrin. The cells may be mobilized from bone marrow. The antisense compound is: 5?-MeCMeUG AGT MeCTG TTT MeUMeCMeC AMeUMeU MeCMeU-3? wherein, (a) each of the 19 internucleotide linkages of the oligonucleotide is an O,O-linked phosphorothioate diester; (b) the nucleotides at the positions 1 to 3 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; (c) the nucleotides at the positions 4 to 12 from the 5? end are 2?-deoxyribonucleosides; (d) the nucleotides at the positions 13 to 20 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; and (e) all cytosines are 5-methylcytosines (MeC), or a pharmaceutically acceptable salt thereof.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.

Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Abstract: A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.

Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.

Abstract: A semiconductor device includes a control signal generation circuit and an input/output (I/O) control circuit. The control signal generation circuit generates first and second read control signals and first and second write control signals. One of the first and second read control signals and one of the first and second write control signals is selectively enabled according to a combination of first and second addresses for selecting a first I/O line or a second I/O line. The I/O control circuit outputs read data loaded on first and second internal I/O lines through any one of the first and second I/O lines in response to the first and second read control signals. In addition, the I/O control circuit outputs input data through any one of the first and second I/O lines in response to the first and second write control signals.

Abstract: An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.

Abstract: A DBI (Data Bus Inversion) controller may be provided. The DBI controller may include an address generation circuit configured to generate a DBI address from an input address. The DBI controller may include a DBI flag signal input and output (input/output) circuit configured to input/output a DBI flag signal in order to write the DBI flag signal to a memory cell corresponding to the DBI address or read the DBI flag signal from the memory cell corresponding to the DBI address, based on a command.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

Abstract: Described herein are methods for treating hematological malignancies and/or solid tumors in a subject using inhibitors of integrin alpha 6. In some embodiments, the inhibitors are monoclonal antibodies. The antibodies may be conjugated to additional therapeutic agents. The antibodies may be co-administered sequentially or simultaneously with additional therapeutic agents.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.