Patents by Inventor Yong Mi
Yong Mi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210303391Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Applicant: SK hynix Inc.Inventors: Jae In LEE, Yong Mi KIM
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Patent number: 11098056Abstract: Described herein is a compound of Formula (I), and pharmaceutically acceptable salts thereof. Also described herein are compositions and the use of such compositions in methods of treating a variety of diseases and conditions, in particular Krabbe's Disease (KD) and Metachromatic leukodystrophy (MLD).Type: GrantFiled: October 1, 2019Date of Patent: August 24, 2021Assignee: GENZYME CORPORATIONInventors: Sungtaek Lim, Robert H. Barker, Jr., Mary A. Cromwell, Elina Makino, Bradford Hirth, John Jiang, Sachin Maniar, Mark Munson, Yong-Mi Choi, Sukanthini Thurairatnam, Kwon Yon Musick, James Pribish, Michael Angelastro
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Patent number: 11080130Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.Type: GrantFiled: December 31, 2019Date of Patent: August 3, 2021Assignee: SK hynix Inc.Inventors: Jae In Lee, Yong Mi Kim
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Patent number: 11041156Abstract: A method for mobilizing leukemia cells which are ?4 integrin positive to the peripheral blood of a human subject, the method comprising administering to the human subject an effective amount of an antisense compound to ?4 integrin. The cells may be mobilized from bone marrow. The antisense compound is: 5?-MeCMeUG AGT MeCTG TTT MeUMeCMeC AMeUMeU MeCMeU-3? wherein, (a) each of the 19 internucleotide linkages of the oligonucleotide is an O,O-linked phosphorothioate diester; (b) the nucleotides at the positions 1 to 3 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; (c) the nucleotides at the positions 4 to 12 from the 5? end are 2?-deoxyribonucleosides; (d) the nucleotides at the positions 13 to 20 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; and (e) all cytosines are 5-methylcytosines (MeC), or a pharmaceutically acceptable salt thereof.Type: GrantFiled: May 4, 2018Date of Patent: June 22, 2021Assignees: Antisense Therapeutics Ltd, Children's Hospital of Los AngelesInventors: George Tachas, Yong-Mi Kim
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Patent number: 10964406Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.Type: GrantFiled: May 17, 2018Date of Patent: March 30, 2021Assignee: SK hynix Inc.Inventors: Young Ook Song, Yong Mi Kim, Chang Hyun Kim
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Publication number: 20200379840Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.Type: ApplicationFiled: December 31, 2019Publication date: December 3, 2020Applicant: SK hynix Inc.Inventors: Jae In LEE, Yong Mi KIM
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Patent number: 10698764Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.Type: GrantFiled: August 23, 2018Date of Patent: June 30, 2020Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Yong Mi Kim
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Patent number: 10613928Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates a first error scrub control signal and a second error scrub control signal according to a logic level combination of an error code including information on the error occurrence number of times. The second semiconductor device performs an error scrub operation of a memory area on a first cycle time in response to the first error scrub control signal during a refresh operation and performs the error scrub operation of the memory area on a second cycle time in response to the second error scrub control signal during the refresh operation.Type: GrantFiled: July 25, 2018Date of Patent: April 7, 2020Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Yong Mi Kim
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Publication number: 20200102324Abstract: Described herein is a compound of Formula (I), and pharmaceutically acceptable salts thereof. Also described herein are compositions and the use of such compositions in methods of treating a variety of diseases and conditions, in particular Krabbe's Disease (KD) and Metachromatic leukodystrophy (MLD).Type: ApplicationFiled: October 1, 2019Publication date: April 2, 2020Inventors: Sungtaek LIM, Robert H. BARKER, JR., Mary A. CROMWELL, Elina MAKINO, Bradford HIRTH, John JIANG, Sachin MANIAR, Mark MUNSON, Yong-Mi CHOI, Sukanthini THURAIRATNAM, Kwon Yon MUSICK, James PRIBISH, Michael ANGELASTRO
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Patent number: 10572341Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.Type: GrantFiled: August 28, 2017Date of Patent: February 25, 2020Assignee: SK hynix Inc.Inventors: Kihun Kwon, Yong Mi Kim, Jaeil Kim
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Patent number: 10430274Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.Type: GrantFiled: September 26, 2017Date of Patent: October 1, 2019Assignee: SK hynix Inc.Inventors: Jae In Lee, Yong Mi Kim
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Patent number: 10422064Abstract: A washing apparatus and control method where the washing apparatus comprises a door configured to open and close the entrance; a tub inside a main body; a diaphragm configured to connect the entrance with the opening; and a drum rotatably provided inside the tub. The washing apparatus includes a door washing nozzle to inject water for a first time in a first section and then to inject the water for a second time in a second section when a washing mode of the diaphragm is entered. The washing mode of the diaphragm including the first section in which the drum in a stopped state is accelerated to arrive at a first target rotation speed less than a second target rotation speed and the second section in which the drum at the first target rotation speed is accelerated to arrive at the second target rotation speed.Type: GrantFiled: February 17, 2017Date of Patent: September 24, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su Jin Seong, Hyun Sook Kim, Woo Kyung Jung, Ja Yeon Seo, Seung-Mok Lee, Yu Ri Lee, Jong Ho Lee, Yong Mi Jung
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Patent number: 10419025Abstract: A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.Type: GrantFiled: August 15, 2017Date of Patent: September 17, 2019Assignee: SK hynix, Inc.Inventors: Jae In Lee, Yong Mi Kim
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Patent number: 10379947Abstract: A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.Type: GrantFiled: June 30, 2017Date of Patent: August 13, 2019Assignee: SK HYNIX INC.Inventors: Jae In Lee, Yong Mi Kim
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Publication number: 20190188075Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.Type: ApplicationFiled: August 23, 2018Publication date: June 20, 2019Inventors: Chang Hyun KIM, Yong Mi KIM
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Publication number: 20190188072Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates a first error scrub control signal and a second error scrub control signal according to a logic level combination of an error code including information on the error occurrence number of times. The second semiconductor device performs an error scrub operation of a memory area on a first cycle time in response to the first error scrub control signal during a refresh operation and performs the error scrub operation of the memory area on a second cycle time in response to the second error scrub control signal during the refresh operation.Type: ApplicationFiled: July 25, 2018Publication date: June 20, 2019Inventors: Chang Hyun KIM, Yong Mi KIM
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Patent number: 10319455Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.Type: GrantFiled: July 3, 2017Date of Patent: June 11, 2019Assignee: SK HYNIX INC.Inventors: Yong Mi Kim, Jae Il Kim
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Publication number: 20190164626Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.Type: ApplicationFiled: May 17, 2018Publication date: May 30, 2019Inventors: Young Ook SONG, Yong Mi KIM, Chang Hyun KIM
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Patent number: 10289485Abstract: An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.Type: GrantFiled: May 31, 2017Date of Patent: May 14, 2019Assignee: SK hynix Inc.Inventors: Jae Woong Yun, Yong Mi Kim, Chang Hyun Kim
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Patent number: 10181863Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.Type: GrantFiled: February 10, 2017Date of Patent: January 15, 2019Assignee: SK hynix Inc.Inventors: Jae Woong Yun, Yong Mi Kim, Chang Hyun Kim