Abstract: The present invention relates to a series of substituted 3-aminopropane phosphinic acid derivatives of formula I: wherein R, R1, P1, P2 and P3 are as defined herein. The compounds of this invention are useful in treating a variety of diseases including but not limited to depression, anxiety, certain psychiatric symptoms, cognitive impairment and schizophrenia.

Abstract: A negative active material containing super-conductive nanoparticles coated with a high capacity negative material and a lithium battery including the same are provided, wherein the super-conductive nanoparticles have a structure in which polycyclic nano-sheets are stacked upon one another along a direction perpendicular to a first plane. The polycyclic nano-sheets include hexagonal rings of six carbons atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L1. L2 is a distance between a third carbon and a fourth carbon, and the arrangement of the polycyclic nano-sheets is such that L1?L2. The super-conductive nanoparticle is used as a negative active material in a lithium battery, and the super-conductive nanoparticle increases the capacity, thereby improving the capacity and lifespan of the lithium battery.

Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.

Abstract: The present invention relates to substituted 2-amino-N-(4-fluoro-3-{1-[1-(alkyl)-1H-indole-3-carbonyl]-piperidin-4-yl}-benzyl)-acetamides (compounds of formula I) compositions thereof, and their use in the treatment of inflammatory diseases.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract: Disclosed is a method for determining the spatial location of a conducting wire and an aerial earth wire of a power transmission line, so as to solve the problem that the method in the prior art is not applicable to determining the spatial location of the conducting wire and the aerial earth wire of the conventional power transmission line with respect to lightning shielding failures.

Abstract: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.

Abstract: A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A lithium titanium oxide for an anode active material of a lithium rechargeable battery, wherein a X-ray diffraction (XRD) spectrum has a first peak of Li4Ti5O12 and a second peak, and A50-55/A78-80 is in a predetermined range, as a result of XRD analysis, where A78-80 is an Area of the first peak and A50-55 is an Area of the second peak in XRD.

Abstract: A negative electrode active material including nanometal particles and super-conductive nanoparticles and a lithium battery including the same.

Abstract: The present invention is directed to a method for the preparation of 2,2,2-trifluoro-n-(4-fluoro-3-pyridin-4-yl-benzyl)-acetamide hydrochloride of the formula: and reaction intermediates used in the method.

Abstract: A composite anode active material includes matrix particles including lithium titanate; and at least one nanoparticle dispersed in the matrix particles. The at least one nanoparticle includes at least one selected from the group a metal capable of forming alloys with lithium and a non-transition metal oxide.

Abstract: A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.

Abstract: A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.