Abstract: A method for mobilizing leukemia cells which are ?4 integrin positive to the peripheral blood of a human subject, the method comprising administering to the human subject an effective amount of an antisense compound to ?4 integrin. The cells may be mobilized from bone marrow. The antisense compound is: 5?-MeCMeUG AGT MeCTG TTT MeUMeCMeC AMeUMeU MeCMeU-3? wherein, (a) each of the 19 internucleotide linkages of the oligonucleotide is an O,O-linked phosphorothioate diester; (b) the nucleotides at the positions 1 to 3 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; (c) the nucleotides at the positions 4 to 12 from the 5? end are 2?-deoxyribonucleosides; (d) the nucleotides at the positions 13 to 20 from the 5? end are 2?-O-(2-methoxyethyl) modified ribonucleosides; and (e) all cytosines are 5-methylcytosines (MeC), or a pharmaceutically acceptable salt thereof.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.

Abstract: A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.

Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.

Abstract: A semiconductor device includes a control signal generation circuit and an input/output (I/O) control circuit. The control signal generation circuit generates first and second read control signals and first and second write control signals. One of the first and second read control signals and one of the first and second write control signals is selectively enabled according to a combination of first and second addresses for selecting a first I/O line or a second I/O line. The I/O control circuit outputs read data loaded on first and second internal I/O lines through any one of the first and second I/O lines in response to the first and second read control signals. In addition, the I/O control circuit outputs input data through any one of the first and second I/O lines in response to the first and second write control signals.

Abstract: An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.

Abstract: A DBI (Data Bus Inversion) controller may be provided. The DBI controller may include an address generation circuit configured to generate a DBI address from an input address. The DBI controller may include a DBI flag signal input and output (input/output) circuit configured to input/output a DBI flag signal in order to write the DBI flag signal to a memory cell corresponding to the DBI address or read the DBI flag signal from the memory cell corresponding to the DBI address, based on a command.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

Abstract: A washing apparatus and control method where the washing apparatus comprises a door configured to open and close the entrance; a tub inside a main body and having an opening corresponding to an entrance to the main body; a diaphragm configured to connect the entrance with the opening; a drum rotatably provided inside the tub; a door washing nozzle provided on the diaphragm to inject washing water to the door. The door washing nozzle is controlled to inject the washing water for a first time in a first section and inject the washing water for a second time in a second section when a washing mode of the diaphragm including the first section at which the drum in a stopped state arrives at a first target rotation speed and the second section at which the drum rotated at the first target rotation speed arrives at a second target rotation speed.

Abstract: Described herein are methods for treating hematological malignancies and/or solid tumors in a subject using inhibitors of integrin alpha 6. In some embodiments, the inhibitors are monoclonal antibodies. The antibodies may be conjugated to additional therapeutic agents. The antibodies may be co-administered sequentially or simultaneously with additional therapeutic agents.

Abstract: A composite anode active material includes matrix particles including lithium titanate; and at least one nanoparticle dispersed in the matrix particles. The at least one nanoparticle includes at least one selected from the group a metal capable of forming alloys with lithium and a non-transition metal oxide.

Abstract: A secondary particle and a lithium battery including the same are provided wherein the secondary particle includes a plurality of primary particles and each primary particle contains n polycyclic nano-sheets disposed upon one another. The polycyclic nano-sheets include hexagonal rings of six carbon atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L1. L2 is a distance between a third carbon and a fourth carbon, and the arrangement of the polycyclic nano-sheets is such that L1?L2. The secondary particle is used as a negative active material in the lithium battery, and the secondary particle contains pores, thereby allowing for effective intercalating and deintercalating of the lithium ions into the secondary particle to impart improved capacity and cycle lifespan.

Abstract: A negative electrode for a lithium secondary battery that includes, as a negative active material, a lithium titanate (Li4Ti5O12) compound containing 0.004 parts by weight or less of phosphorous (P) and 0.007 parts by weight or less of potassium (K) based on 100 parts by weight of lithium titanate, a binder, and a conductive agent, and a lithium secondary battery including the negative electrode.

Abstract: A negative active material comprising lithium titanate oxide having an area ratio of a diffraction peak of a (111) plane that appears at 2?=18.3°±0.4 to a diffraction peak of a (311) plane that appears at 2?=35.5°±0.4, in an XRD spectrum, in the range of about 2.2:1 to about 5.5:1, a negative electrode comprising the negative active material, a lithium secondary battery comprising the negative electrode, and a method of preparing the negative active material.

Abstract: A negative electrode active material, a method of preparing the negative electrode active material and a lithium secondary battery including the negative electrode active material are disclosed. A negative electrode active material includes a lithium titanate, wherein a portion of lithium of the lithium titanate is substituted by at least one selected from the group consisting of Sr, Ba, a mixture thereof and an alloy thereof, and thus a lithium secondary battery including the negative electrode active material may improve high-rate discharge characteristics.

Abstract: A spherical primary particle of a lithium titanium oxide of which average diameter is in the range of about 1 to about 20 ?m, a method of preparing the spherical primary particle of the lithium titanium oxide, and a lithium rechargeable battery including the spherical primary particle of the lithium titanium oxide.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A method for sterilizing microbial cells is provided. According to the method, microbial cells or a culture containing microbial cells are treated with a polyethylene glycol-based nonionic surfactant so that almost all of the microbial cells are sterilized while the enzyme activity expressed in the microbial cells is maintained at a high level. A method for sterilizing microbial cells and a material containing the sterilized microbial cells, in which the microbial cells are sterilized using a polyethylene glycol-based nonionic surfactant, can be used for foods so that the microbial cells are sterilized to be used in food production. Further, a material containing sterilized microbial cells can be used in processes for preparing tagatose, in which Corynebacterium genus microbial cells that produce Galactose and/or Arabinose isomerase are sterilized using a polyethylene glycol-based nonionic surfactant.