Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.

Abstract: A negative active material containing super-conductive nanoparticles coated with a high capacity negative material and a lithium battery including the same are provided, wherein the super-conductive nanoparticles have a structure in which polycyclic nano-sheets are stacked upon one another along a direction perpendicular to a first plane. The polycyclic nano-sheets include hexagonal rings of six carbons atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L1. L2 is a distance between a third carbon and a fourth carbon, and the arrangement of the polycyclic nano-sheets is such that L1?L2. The super-conductive nanoparticle is used as a negative active material in a lithium battery, and the super-conductive nanoparticle increases the capacity, thereby improving the capacity and lifespan of the lithium battery.

Abstract: A lithium titanate aggregate and a method of preparing the same. In the lithium titanate aggregate, a single primary particle has a median diameter (D50) of about 8×10?2 ?m to about 3.1×10?1 ?m, and has a spherical shape. In addition, an amount of primary particles having a diameter of about 55 nm to about 85 nm is about 55% to about 75% of all primary particles.

Abstract: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: The present invention is directed to an indole benzylamine compound of formula I: useful as an inhibitor of tryptase. In addition, the present invention is directed to the use of the compound for treating a patient suffering from, or subject to, a physiological condition in need of amelioration by inhibition of tryptase, comprising administering to the patient of a therapeutically effective amount of the compound, and to a pharmaceutical composition comprising a pharmaceutically effective amount of the compound of formula I, and a pharmaceutically acceptable carrier.

Abstract: A secondary particle and a lithium battery including the same are provided wherein the secondary particle includes a plurality of primary particles and each primary particle contains n polycyclic nano-sheets disposed upon one another. The polycyclic nano-sheets include hexagonal rings of six carbon atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L1. L2 is a distance between a third carbon and a fourth carbon, and the arrangement of the polycyclic nano-sheets is such that L1?L2. The secondary particle is used as a negative active material in the lithium battery, and the secondary particle contains pores, thereby allowing for effective intercalating and deintercalating of the lithium ions into the secondary particle to impart improved capacity and cycle lifespan.

Abstract: A negative electrode active material including nanometal particles and super-conductive nanoparticles and a lithium battery including the same.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A spherical primary particle of a lithium titanium oxide of which average diameter is in the range of about 1 to about 20 ?m, a method of preparing the spherical primary particle of the lithium titanium oxide, and a lithium rechargeable battery including the spherical primary particle of the lithium titanium oxide.

Abstract: A lithium titanium oxide for an anode active material of a lithium rechargeable battery, wherein a X-ray diffraction (XRD) spectrum has a first peak of Li4Ti5O12 and a second peak, and A50-55/A78-80 is in a predetermined range, as a result of XRD analysis, where A78-80 is an Area of the first peak and A50-55 is an Area of the second peak in XRD.

Abstract: A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: A motion-vector operation device includes an upper memory composed of first and second banks that store motion vectors of a lower block group belonging to a macroblock, a left memory storing motion vectors of a right block group belonging to a macroblock, and an estimator predicting a motion vector of a current block with reference to the motion vectors stored in the first and second banks of the upper memory and the left memory in accordance with an operation mode and a position of the current block in a super macroblock.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: The present invention relates to new heterocyclic compounds containing nitrogen atoms or pharmaceutically acceptable salts thereof, a process for the preparation thereof, and a pharmaceutical composition comprising the same for treatment of cancer. The compounds according to the present invention induce DNA damage due to reactive oxygen species to activate c-abl and p53, induce RhoB to generate apoptosis, and induce cell death by down-regulating Bcl2 involved in cell survival, which is generated by dysregulated signals via the mitochondria pathway, thereby inhibiting tumor cell growth and inducing apoptosis. Accordingly, the composition according to the present invention can be used to treat cancer.

Abstract: A plasma display panel for improving luminous efficiency including first and second substrates facing each other; barrier ribs partitioning a space between the first and second substrates to define discharge cells; address electrodes on the first substrate and extending along a first direction to correspond to the discharge cells; first and second electrodes extending along a second direction crossing the first direction on the second substrate to define a discharge gap at centers of the discharge cells; a dielectric layer covering the first and second electrodes; and a protective layer covering the dielectric layer. The dielectric layer includes a first section in the discharge gap and a portion adjacent to the discharge gap in the first direction and having a smaller dielectric constant, and a second section at either side of the first dielectric constant section in the first direction and having a larger dielectric constant.

Abstract: The present invention relates to certain esters of substituted 3-aminopropane phosphinic acid derivatives of formula I: wherein R, R1 and R2 are as defined herein. The compounds of this invention are useful in treating a variety of diseases including but not limited to depression, anxiety, certain psychiatric symptoms, cognitive impairment and schizophrenia.