Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.

Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.

Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.

Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.

Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.

Abstract: A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.