Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: An integrated chip comprises a substrate, an isolation structure and a gate structure. The isolation structure is disposed in the substrate and enclosing an active region in the substrate. The active region comprises a source region and a drain region separated by a channel region along a first direction. The gate structure is disposed over the channel region and comprising a first gate electrode region and a second gate electrode region arranged one next to another laterally along a second direction perpendicular to the first direction. The first gate electrode region has a first composition, and the second gate electrode region has a second composition different than the first composition.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: An integrated chip comprises a substrate, an isolation structure and a gate structure. The isolation structure comprises one or more dielectric materials within the substrate and has sidewalls defining an active region in the substrate. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source, drain and channel regions respectively have first, second and third widths along a second direction perpendicular to the first direction. The third width is larger than the first and second widths. The gate structure comprises a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device, as well as a method for forming the IC. In some embodiments, the IC comprises a memory cell structure including a pair of control gates respectively separated from a substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates. A memory test structure includes a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates. The memory test structure further includes a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.