Patents by Inventor Yong-Shiuan Tsair
Yong-Shiuan Tsair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10269815Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.Type: GrantFiled: April 27, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: ShihKuang Yang, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
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Publication number: 20190067305Abstract: A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: HUNG-LING SHIH, YONG-SHIUAN TSAIR, PO-WEI LIU, WEN-TUO HUANG, YU-LING HSU, CHIEH-FEI CHIU
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Publication number: 20180315764Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90° <?1<115° measured from the upper surface of the erase gate.Type: ApplicationFiled: April 27, 2017Publication date: November 1, 2018Inventors: ShihKuang YANG, Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Wen-Tuo HUANG, Yu-Ling HSU, Yong-Shiuan TSAIR
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Publication number: 20180197873Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: ApplicationFiled: March 7, 2018Publication date: July 12, 2018Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. Yang
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Patent number: 9997524Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.Type: GrantFiled: September 21, 2016Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Tsun-Kai Tsao, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
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Publication number: 20180151375Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and. the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.Type: ApplicationFiled: October 5, 2017Publication date: May 31, 2018Inventors: Yu-Ling HSU, Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Wen-Tuo HUANG, Yong-Shiuan TSAIR, Shihkuang YANG
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Patent number: 9929167Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: GrantFiled: July 13, 2016Date of Patent: March 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Kai Tsao, Hung-Ling Shih, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair, S. K. Yang
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Publication number: 20180061847Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.Type: ApplicationFiled: September 21, 2016Publication date: March 1, 2018Inventors: Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Tsun-Kai TSAO, Wen-Tuo HUANG, Yu-Ling HSU, Yong-Shiuan TSAIR
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Publication number: 20180019251Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. Yang
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Patent number: 9728543Abstract: A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.Type: GrantFiled: August 15, 2016Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming Pan, Chiang-Ming Chuang, Kun-Tsang Chuang, Po-Wei Liu, Yong-Shiuan Tsair
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Patent number: 9646980Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.Type: GrantFiled: March 4, 2016Date of Patent: May 9, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
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Publication number: 20160225780Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.Type: ApplicationFiled: March 4, 2016Publication date: August 4, 2016Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
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Patent number: 9287282Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.Type: GrantFiled: January 28, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
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Patent number: 9287280Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.Type: GrantFiled: July 9, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsun-Kai Tsao, Yong-Shiuan Tsair, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang
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Publication number: 20160035736Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.Type: ApplicationFiled: July 29, 2014Publication date: February 4, 2016Inventors: Hung-Ling Shih, Yong-Shiuan Tsair, Tsun-Kai Tsao, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu
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Patent number: 9252150Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.Type: GrantFiled: July 29, 2014Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Ling Shih, Yong-Shiuan Tsair, Tsun-Kai Tsao, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu
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Publication number: 20160013195Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.Type: ApplicationFiled: July 9, 2014Publication date: January 14, 2016Inventors: Tsun-Kai Tsao, Yong-Shiuan Tsair, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang
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Patent number: 9159735Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.Type: GrantFiled: July 18, 2013Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen
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Publication number: 20150214237Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.Type: ApplicationFiled: January 28, 2014Publication date: July 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
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Publication number: 20150021679Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.Type: ApplicationFiled: July 18, 2013Publication date: January 22, 2015Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen