Abstract: A sealing member includes a body having a ring shape, a lower contacting portion protruding from a lower end of the body and having at least one recess, the recess provided in a lower surface of the lower contacting portion and extending in a radial direction of the body, and an outer contacting portion protruding outwards from the body along an outer side portion of the body.

Abstract: Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.

Abstract: A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.

Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.

Abstract: A composition for removing photoresist, including an alkyl ammonium fluoride salt in an amount ranging from about 0.5 weight percent to about 10 weight percent, based on a total weight of the composition; an organic sulfonic acid in an amount ranging from about 1 weight percent to about 20 weight percent, based on the total weight of the composition; and a lactone-based solvent in an amount ranging from about 70 weight percent to about 98.5 weight percent, based on the total weight of the composition.

Abstract: A cleaning solution composition includes an organic solvent in which a metal fluoride does not dissolve, at least one fluoride compound that generates bifluoride (HF2?), and deionized water, wherein the deionized water may be included in a concentration of 1.5 wt % or lower based on the total weight of the cleaning solution composition.

Abstract: A spot heater and a device for cleaning a wafer using the same are provided. The wafer cleaning device includes a heater chuck on which a wafer is mounted, the heater chuck configured to heat a bottom surface of the wafer; a chemical liquid nozzle configured to spray a chemical liquid on a top surface of the wafer for etching; and a spot heater configured to heat a spot of the top surface of the wafer.

Abstract: A system for removing a photoresist includes a solution storage configured to store a preliminary photoresist removal solution, a solution activation unit configured to convert the preliminary photoresist removal solution from the solution storage into an activated photoresist removal solution, and a photoresist removal unit configured to receive the activated photoresist removal solution from the solution activation unit, and configured to load a substrate including a photoresist pattern formed thereon.

Abstract: A cleaning solution composition includes an organic solvent in which a metal fluoride does not dissolve, at least one fluoride compound that generates bifluoride (HF2?), and deionized water, wherein the deionized water may be included in a concentration of 1.5 wt % or lower based on the total weight of the cleaning solution composition.

Abstract: A sealing member includes a body having a ring shape, a lower contacting portion protruding from a lower end of the body and having at least one recess, the recess provided in a lower surface of the lower contacting portion and extending in a radial direction of the body, and an outer contacting portion protruding outwards from the body along an outer side portion of the body.

Abstract: A nozzle may include a nozzle body, a conductive line and a resistance-measuring member. The nozzle body may include a plurality of injecting holes. The conductive line may be disposed along the injecting holes. The resistance-measuring member may be configured to measure a resistance of the conductive line to detect a deformation of the injecting holes.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

Abstract: A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.