Patents by Inventor Yong Sung Eom

Yong Sung Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130146342
    Abstract: The present invention relates to a pattern-forming composition used to form a conductive circuit pattern. The pattern-forming composition comprises Cu powders, a solder for electrically coupling the Cu powders, a polymer resin, a curing agent and a reductant. According to the present invention, a circuit pattern having superior conductivity can be formed at low cost.
    Type: Application
    Filed: September 12, 2012
    Publication date: June 13, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Kwang-Seong Choi, Hyun-cheol Bae, Jung Hyun Noh, Jong Tae Moon
  • Patent number: 8420722
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 16, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Jong Tae Moon, Sangwon Oh, Keonsoo Jang
  • Publication number: 20120288983
    Abstract: Disclosed is a method for manufacturing a dye sensitized solar cell module. The method includes putting at least one or more heating-wires on an upper portion of an electrode of each solar cell sub-module; applying a metal paste on the upper portion of the electrode including at least one or more heating-wires; and heating and curing the metal paste by after overlapping the electrodes of a plurality of solar cell sub-modules each other, allowing a current to flow to at least one or more heating-wires.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 15, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Moo Jung Chu, Ju Mi Kim, Yong Sung Eom, Ah Ram Jeon, Jong Tae Moon
  • Publication number: 20120240727
    Abstract: Disclosed is a method of manufacturing a solder powder having a diameter of sub-micrometers or several micrometers, the method including: mixing solder powder having a diameter of 10 to 1000 micrometers with a polymer resin to obtain a mixture; heating the mixture to a temperature higher than a melting point of the solder powder in the mixture; applying ultrasonic waves to the heated mixture so that the diameter of the solder powder becomes 0.1 to 10 micrometers; and cooling the mixture to the room temperature without exposing the solder powder of 0.1 to 10 micrometers to the air.
    Type: Application
    Filed: February 2, 2012
    Publication date: September 27, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Jong Tae MOON, Kwang Seong CHOI
  • Publication number: 20120222738
    Abstract: A conductive composition for a front electrode busbar of a silicon solar cell includes a metallic powder, a solder powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing a front electrode busbar of a silicon solar cell includes applying the composition to the front surface of the silicon solar cell wherein its front electrode finger line is formed. A substrate includes a front electrode busbar of a silicon solar cell, formed with a conductive composition. A silicon solar cell includes one or more electrodes containing a conductive composition including a conductive powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing the silicon solar cell includes forming a first electrode array with a first conductive composition, forming a second electrode, and forming a third electrode with a third conductive composition.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 6, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo Young OH, Yong Sung Eom, Jong Tae Moon, Kwang Seong Choi
  • Patent number: 8211745
    Abstract: Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: July 3, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Jong Tae Moon, Kwang-Seong Choi
  • Publication number: 20120161326
    Abstract: Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 28, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Seong Choi, Yong Sung Eom, Hyun-cheol Bae, Jong Tae Moon
  • Publication number: 20120164787
    Abstract: Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 28, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Tae Moon, Yong Sung Eom, Hyun-Cheol Bae
  • Patent number: 8044757
    Abstract: Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 25, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun-Cheol Bae, Kwang-Seong Choi, Yong Sung Eom, Jong Tae Moon, Moo Jung Chu, Jong-Hyun Lee
  • Patent number: 8030200
    Abstract: A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-Cheol Bae, Jong-Hyun Lee, Jong Tae Moon
  • Publication number: 20110227228
    Abstract: Provided is a filling composition. The filling composition includes: a first particle including Cu and/or Ag; a second particle electrically connecting the first particles; and a resin containing a high molecular compound, a hardener, and a reducer, in which the first and second particles are dispersed, wherein the hardener includes amine and/or anhydride, and the reducer includes carboxyl.
    Type: Application
    Filed: September 21, 2010
    Publication date: September 22, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Jong Tae Moon, Kwang-Seong Choi, Hyun-cheol Bae, Jong Jin Lee
  • Patent number: 7985697
    Abstract: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: July 26, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong Tae Moon, Yong Sung Eom, Min Ji Lee, Hyun Kyu Yu
  • Publication number: 20110089577
    Abstract: Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.
    Type: Application
    Filed: April 16, 2010
    Publication date: April 21, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Jong Tae Moon, Kwang-Seong Choi
  • Publication number: 20110050499
    Abstract: Provided is a sensing device having a multi beam antenna array. The sensing device includes an antenna array including a plurality of antennas, a plurality of low noise amplifiers respectively connected to the antennas to amplify radio frequency signals received from the respective antennas, a delay line box including a plurality of delay lines, each delay line delaying the signals amplified by the low noise amplifiers for a predetermined time, and a detector detecting the output signals of the delay ling box.
    Type: Application
    Filed: April 30, 2010
    Publication date: March 3, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong Suk JUN, Yong Sung EOM, Hyun Seo KANG, Moo Jung CHU, Soo Young OH
  • Publication number: 20110018670
    Abstract: Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.
    Type: Application
    Filed: December 28, 2009
    Publication date: January 27, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Cheol BAE, Kwang-Seong Choi, Yong Sung Eom, Jong Tae Moon, Moo Jung Chu, Jong-Hyun Lee
  • Publication number: 20100320596
    Abstract: Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.
    Type: Application
    Filed: September 23, 2009
    Publication date: December 23, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-Cheol Bae, Jong-Hyun Lee, Jong Tae Moon
  • Publication number: 20100006625
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Application
    Filed: June 2, 2009
    Publication date: January 14, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Jong Tae MOON, Sangwon OH, Keonsoo JANG
  • Publication number: 20090261481
    Abstract: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate.
    Type: Application
    Filed: September 11, 2008
    Publication date: October 22, 2009
    Applicant: ELECRTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Tae MOON, Yong Sung Eom, Min Ji Lee, Hyun Kyu Yu
  • Patent number: 7520682
    Abstract: The present invention provides a transceiver module having advantages of minimizing the number of optical parts by using an optical collimator to which a lens having the same shape as a diameter of an optical fiber is attached on a light input/output end. An transceiver module according to the present invention includes, laser diode for generating an optical signal to transmit, a first photodiode for controlling the laser diode, a second and third photodiodes for receiving an optical signal of a first and second wavelengths, and an optical collimator formed at a light input/output end. On the optical collimator, a lens having an optical fiber shape is attached in a direction the light proceeds.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 21, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Sung Eom, Jong-Tae Moon, Ho-Gyeong Yun, Byung-Seok Choi, Jong-Hyun Lee
  • Patent number: 7244923
    Abstract: Provided are a surface emitting laser device having an optical sensor, and an optical waveguide device employing the same. The surface emitting laser device having an optical sensor includes a surface emitting laser formed on a substrate and generating a laser beam to output it to outside, and an optical sensor formed adjacent to the surface emitting laser on the substrate and receiving external light. In the surface emitting laser device having the optical sensor, and the optical waveguide device employing the same, the surface emitting laser and the optical sensor are simultaneously integrated, however, the performance of the surface emitting laser is unaffected by the optical sensor and the optical sensor operates separately, exhibits high performance, and can respond within a wide wavelength band.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: July 17, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Woo Song, Jong Hee Kim, Yong Sung Eom