Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

Abstract: Disclosed is an airbag device which varies and deploys a shape of an airbag cushion according to an attitude of a seat and a posture of a passenger to safely protect the passenger. In particular, the airbag device includes: a first tether of which one end is connected to an airbag housing, a second tether which includes a first portion connected between the other end of the first tether and a front surface of the airbag cushion, and a second portion connected between the other end of the first tether and the airbag housing to have a margin length, and a tether cutter provided to cut the first tether and configured to perform one deployment mode of a first deployment mode and a second deployment mode according to whether first tether is cut.

Abstract: A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.

Abstract: A micro-light emitting diode device includes a backplane that includes drive circuits and a first bonding layer, and an array of micro-LEDs that includes an array of semiconductor mesa structures and a second bonding layer. The first bonding layer includes a first dielectric layer, and first metal interconnects that are at least partially in the first dielectric layer and electrically connected to the drive circuits. The second bonding layer includes a second dielectric layer, and second metal interconnects that are at least partially in the second dielectric layer and electrically connected to the array of semiconductor mesa structures. The first bonding layer is bonded to the second bonding layer. At least one of the first dielectric layer or the second dielectric layer includes a first dielectric material characterized by a thermal conductivity greater than 50 W/(m·K) at room temperature, such as AlN.

Abstract: The present disclosure relates to a method for non-oxidative direct conversion of methane. Specifically, in the method, a methane/hydrogen gas is introduced into an Inconel 600 reactor at a superficial velocity of 100 to 200 cm·min?1 and a catalyst is not externally introduced into the reactor. Under the conditions, a non-oxidative direct methane conversion reaction is performed in the Inconel 600 reactor. The method maximizes the reaction rate, minimizes coke formation, and increases the yields of C2 hydrocarbon compounds and aromatic compounds.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: A device is provided to include: a transceiver configured to transmit and receive data; and a skip ordered set (SKP OS) control logic in communication with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and a data block to a link connecting to an external device and including a plurality of lanes. The SKP OS control logic is configured to increase or decrease transmission interval of the SKP OS based on a transmission history of the SKP OS, in response to an entry of the link to a recovery state that is used to recover the link from an error.

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

Abstract: Provided herein may be an interface device and a method of operating the same. The interface device may include a first port configured to enable communication with a host, a second port configured to enable communication with the host, and a function manager including a plurality of variable functions that are selectively assignable to at least one of the first port and the second port.

Abstract: A display device includes a display area and a pad area. The display device may include a pixel on a base layer in the display area, the pixel including a light emitting element, and pads on the base layer in the pad area. The pads may include pad lines including first and second pad lines and first and second electrode parts. The pads may include a first contact area and a second contact area. The first pad line and the second pad line may be electrically connected to each other in the first contact area. The second pad line and the second electrode part may be electrically connected in the second contact area. The first electrode part may overlap the second pad line in a plan view. The first and second electrode parts may be electrically separated from each other by a pad insulating pattern.

Abstract: A Peripheral Component Interconnect express (PCIe) device includes: a plurality of ports forming a plurality of lanes; and a link controller configured to set a link including the plurality of lanes to allocate non-sequential lane numbers to lanes adjacent to each other among the plurality of lanes.

Abstract: Disclosed is a battery cell, which includes an electrode assembly including a cell body and an electrode tab provided to at least one side of the cell body, a cell case configured to accommodate the electrode assembly therein, an electrode lead coupled to the electrode tab and extending from the cell case, and a tab protection module accommodated in the cell case and configured to cover at least a portion of the electrode tab, the tab protection module including a lead positioning guide and a corresponding positioning guide insert portion adapted to receive the positioning guide insert portion, wherein the positioning guide insert portion is configured to couple to the electrode lead to guide a position of the electrode lead relative to the cell case.

Abstract: The present specification discloses a novel benzyloxy pyridine derivative compound represented by Chemical Formula 1, a salt thereof, a stereoisomer thereof, a hydrate thereof, or a solvate thereof, and novel uses thereof. The uses comprise the uses in the preparation of a composition for activating autophagy, a composition for activating p62 protein, a composition for inducing oligomerization of p62 protein, or a composition for ameliorating, preventing or treating a disease caused by misfolded protein.

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

Abstract: A secondary battery according to the present invention comprises: an electrode assembly in which a first electrode, a separator, and a second electrode are alternately stacked and wound together; a can provided with an accommodation part that accommodates the electrode assembly therein, the can comprising a first can and a second can, which have cylindrical shapes opened in a direction facing each other; and an insulator configured to insulate an overlapping portion between the first can and the second can. The first can forms a first electrode terminal that directly contacts an end of the first electrode, and the second can forms a second electrode terminal that directly contacts an end of the second electrode.

Abstract: A PCIe device and a method of operating the same are provided. The PCIe device may include a throughput calculator configured to calculate a throughput of each of a plurality of functions, a throughput analysis information generator configured to generate throughput analysis information indicating a result of a comparison between a throughput limit and the calculated throughput, a delay time information generator configured to generate a delay time for delaying a command fetch operation for each function based on the throughput analysis information, a command lookup table storage configured to store command-related information and a delay time of a function corresponding to a target command, the command-related information including information related to the target command to be fetched from a host, and a command fetcher configured to fetch the target command based on the command-related information and the delay time of the corresponding function.