Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: A method for processing a series of database transactions according to an embodiment includes recording a first transaction requested to a first database by a first application, among the plurality of applications, in association with a transaction group ID, recording a second transaction requested to a second database by a second application called by the first application, among the plurality of applications, in association with the transaction group ID, rolling back the second transaction targeted to the second database in response to a determination that an error has occurred during processing of the second transaction, identifying the first transaction based on the transaction group ID and rolling back the first transaction targeted to the first database.

Abstract: A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes according to the present disclosure includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the plurality of lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.

Abstract: A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.

Abstract: An energy storage system includes at least one battery rack including at least two battery modules, a container in which the battery rack is received, an air conditioner including an outside heat exchanger configured to cool a heat exchanger medium having a temperature rise in the container, and a circulation path configured to allow the heat exchanger medium to circulate between the container and the outside heat exchanger, a fire extinguishing unit including a fire extinguishing agent tank configured to detect a temperature of the at least one battery module that is equal to or higher than a predetermined temperature or smoke that is generated in the at least one battery module and feed the fire extinguishing agent to the battery module, and an air conditioner management unit configured to spray the fire extinguishing agent in the fire extinguishing agent tank onto an outer surface of the outside heat exchanger.

Abstract: Provided is a method for determining the wetting degree of a lithium ion battery cell using a low current test. The wetting degree determination method according to the present disclosure includes a) obtaining, as a reference charge profile, a charge profile recorded while charging a reference battery cell having undergone receiving an electrode assembly and an electrolyte solution in a case, assembling and pre-aging with a low current of 0.01 C-rate or less, b) measuring and recording a charge profile while charging another battery cell having undergone receiving an electrode assembly and an electrolyte solution in a case, assembling and pre-aging with a low current of 0.01 C-rate or less in the same way as the reference battery cell, and c) determining the wetting degree of another battery cell relative to the reference battery cell by comparative analysis of the reference charge profile and the measured charge profile.

Abstract: A semiconductor package and manufacturing method is disclosed. The semiconductor package includes a semiconductor chip having a plurality of chip terminals formed on one surface thereof, a redistribution layer electrically connected to the chip terminal and extending outwardly from a side surface of the chip to electrically connect the chip terminal to an external device, an external pad provided on the insulating layer, formed to be in contact with the redistribution layer exposed from the insulating layer to be electrically connected to the redistribution layer, and exposed to an upper side of the insulating layer; an external connection terminal formed on the external pad and contacting an external device, a protective layer formed to surround at least one surface and a side surface of the chip, and an insulating layer formed to cover the redistribution layer.

Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure relates to control a client device using a server device based on context data indicating a circumstance of a user.

Abstract: A sound vibration actuator includes: a casing having an internal space formed by an underside casing part, a side periphery casing part, and a top casing part; a first vibration assembly disposed in the internal space of the casing; a second vibration assembly disposed between the first vibration assembly and the top casing part in such a manner as to be coupled to the top casing part; an elastic member whose one surface coupled to the first vibration assembly; and a third vibration assembly disposed between the first vibration assembly and the underside casing part in such a manner as to be coupled to the underside casing part. The sound vibration actuator includes at least three or more vibration assemblies disposed therein, thereby obtaining at least three or more resonance frequencies.

Abstract: An energy storage apparatus includes at least one battery rack having at least two battery packs; a container configured to accommodate the at least one battery rack; and an air conditioner provided with a coolant supply part, which includes at least two blowout units respectively having a nozzle with a discharge hole through which a coolant is discharged and configured to individually switch a discharge direction of the coolant, toward any, one of the at least two battery packs and individually increase or decrease a discharge amount of the coolant and a control unit configured to adjust the discharge direction and the discharge amount of the coolant of each of the at least two blowout units, and a coolant suction part configured to suck a heated coolant inside the container.

Abstract: The present invention relates to a catalyst for selective hydrogenation of acetylene and a preparation method thereof. More specifically, the catalyst and preparation method maximize the catalytic reaction rate at various reaction temperatures and suppress side reactions to minimize the generation of green oil and cokes and to improve the deactivation rate of a catalyst when preparing ethylene from acetylene. Thus, the catalyst and the preparation method provide a high conversion rate of acetylene and a high ethylene production yield.

Abstract: Disclosed are a composition for depositing a thin film including an organometallic compound including strontium, barium, or a combination thereof; and at least one unshared electron pair-containing compound represented by Chemical Formula 1, a method of manufacturing a thin film using the composition for depositing the thin film, and the thin film manufactured from the composition for depositing the thin film, and a semiconductor device including the thin film.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

Abstract: A Peripheral Component Interconnect Express (PCIe) device performing communication with a host through a PCIe link includes a first physical function, a plurality of second physical functions, and a function mode controller. The first physical function manages the PCIe link and receives function mode control information from the host. Each of the plurality of second physical functions may be enabled or disabled according to a respective operation mode. Based on the function mode control information, the function mode controller sets the operation modes of the plurality of second physical functions to one of an active mode and an inactive mode.

Abstract: A Peripheral Component Interconnect Express (PCIe) function includes an access identification information controller generating first access identification information for allowing an access to the PCIe function, and providing the first access identification information to an assigned system image to which the PCIe function has been assigned, the assigned system image being one of a plurality of system images, a data packet receiver receiving a data packet including target identification information indicating a target system image selected from the plurality of system images from the target system image, and an access allowance determiner determining whether or not to allow an access of the first target system image based on the access identification information and the target identification information.

Abstract: A peripheral component interconnect express (PCIe) device includes a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host. Each function type may be a physical function type, a virtual function type, or a disable function type.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: A composition has effects for promoting endoplasmic reticulum (ER)-phagy, a composition for maintaining ER homeostasis or reducing ER stress, and a pharmaceutical composition for preventing and/or treating ER-stress-related diseases. The composition contains a p62 ligand compound as an active ingredient. The p62 ligand compound can modulate p62 to interact with a receptor associated with autophagic degradation of ER component, modulate oligomerization and/or aggregation of the receptor, modulate formation of autophagosomes, and the like. Thus, uses of p62 ligand compound in inducing ER-autophagy are provided.

Abstract: A display device includes a first electrode and a second electrode spaced apart from each other, each of the first electrode and the second electrode including an electrode base layer, a main electrode layer disposed on the electrode base layer, and an electrode upper layer disposed on a portion of the main electrode layer, a first insulating layer disposed on the first electrode and the second electrode, light-emitting elements disposed on the first electrode and the second electrode on the first insulating layer, a first connecting electrode electrically contacting the light-emitting elements, and a second connecting electrode electrically contacting the light-emitting elements. The first electrode includes a first part, the second electrode includes a second part, and the light-emitting elements are disposed on the first part and the second part.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.