Patents by Inventor Yong Tae Kwon

Yong Tae Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230048456
    Abstract: The present specification relates to an organic light emitting device including Compound (A) represented by Chemical Formula 1 and Compound (B) represented by any one of Chemical Formulae 2 to 4.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 16, 2023
    Applicant: LT MATERIALS CO., LTD.
    Inventors: Su-Jin KWON, Yong-Hui LEE, Ji-Young KIM, Jun-Tae MO, Dong-Jun KIM
  • Patent number: 11545451
    Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 3, 2023
    Assignee: NEPES CO., LTD.
    Inventors: Hyun Sik Kim, Seung Hwan Shin, Yong Tae Kwon, Dong Hoon Seo, Hee Cheol Kim, Dong Soo Lee
  • Publication number: 20220402873
    Abstract: Novel p62 ligand compounds, or a stereoisomer, a solvate, a hydrate, or a prodrug thereof are disclosed. The novel compounds, stereoisomer, solvate, hydrate, or prodrug activates selective autophagy in cells to selectively remove proteins, organelles, and coagulations in the body, and thus can be advantageously used as a pharmaceutical composition for preventing, ameliorating, or treating various proteinopathies. Compositions such as pharmaceutical composition or food compositions containing the novel p62 ligand compounds, stereoisomer, solvate, hydrate, or prodrug thereof as well as uses thereof are disclosed.
    Type: Application
    Filed: September 21, 2020
    Publication date: December 22, 2022
    Applicants: AUTOTAC INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Yong Tae KWON, Chang Hoon JI, Hyun Tae KIM, Jeong Eun NA, Hee Yeon KIM, Min Ju LEE
  • Publication number: 20220352059
    Abstract: A semiconductor package and manufacturing method is disclosed. The semiconductor package includes a semiconductor chip having a plurality of chip terminals formed on one surface thereof, a redistribution layer electrically connected to the chip terminal and extending outwardly from a side surface of the chip to electrically connect the chip terminal to an external device, an external pad provided on the insulating layer, formed to be in contact with the redistribution layer exposed from the insulating layer to be electrically connected to the redistribution layer, and exposed to an upper side of the insulating layer; an external connection terminal formed on the external pad and contacting an external device, a protective layer formed to surround at least one surface and a side surface of the chip, and an insulating layer formed to cover the redistribution layer.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 3, 2022
    Inventors: Jong Heon KIM, Young Mo LEE, Nam Chul KIM, Yong Tae KWON, Chi Jung SONG, Yong Soo KIM, Yong Ho KWON
  • Patent number: 11476211
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 18, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Jun Kyu Lee, Su Yun Kim, Dong Hoon Oh, Yong Tae Kwon, Ju Hyun Nam
  • Publication number: 20220323379
    Abstract: A composition has effects for promoting endoplasmic reticulum (ER)-phagy, a composition for maintaining ER homeostasis or reducing ER stress, and a pharmaceutical composition for preventing and/or treating ER-stress-related diseases. The composition contains a p62 ligand compound as an active ingredient. The p62 ligand compound can modulate p62 to interact with a receptor associated with autophagic degradation of ER component, modulate oligomerization and/or aggregation of the receptor, modulate formation of autophagosomes, and the like. Thus, uses of p62 ligand compound in inducing ER-autophagy are provided.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 13, 2022
    Applicant: PROTECH, INC.
    Inventors: Yong Tae KWON, Chang Hoon JI, Hee Yeon KIM, An Jung HEO, Srinivasrao GANIPISETTI
  • Publication number: 20220298113
    Abstract: The present specification discloses a novel benzyloxy pyridine derivative compound represented by Chemical Formula 1, a salt thereof, a stereoisomer thereof, a hydrate thereof, or a solvate thereof, and novel uses thereof. The uses comprise the uses in the preparation of a composition for activating autophagy, a composition for activating p62 protein, a composition for inducing oligomerization of p62 protein, or a composition for ameliorating, preventing or treating a disease caused by misfolded protein.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 22, 2022
    Applicants: AUTOTAC INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Yong Tae KWON, Hyun Tae KIM, Jeong Eun NA, Chang Hoon JI, Chang An JUNG
  • Patent number: 11450535
    Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 20, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee, Si Woo Lim, Dong-Hoon Oh, Jun-Sung Ma, Tae-Won Kim
  • Publication number: 20220278053
    Abstract: A technical idea of the present disclosure provides a semiconductor package, as a semiconductor package mounted on a circuit board, including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 1, 2022
    Applicant: NEPES CO., LTD.
    Inventors: Ju Hyun NAM, Jun Kyu LEE, Yong Tae KWON, Su Yun KIM, Dong Hoon OH
  • Publication number: 20220165648
    Abstract: Disclosed is a semiconductor package including a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first surface of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second surface of the semiconductor chip; a conductive post disposed outside the semiconductor chip; a first redistribution structure, which is on the first surface of the semiconductor chip and includes a first redistribution insulation layer supporting the conductive stud and the conductive post; a second redistribution structure, which is on the second surface of the semiconductor chip and includes a second redistribution insulation layer disposed on the adhesive layer; and a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 26, 2022
    Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATION
    Inventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba
  • Publication number: 20220148993
    Abstract: Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 12, 2022
    Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATION
    Inventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba
  • Publication number: 20210398869
    Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: December 23, 2021
    Applicant: NEPES CO., LTD.
    Inventors: Su Yun KIM, Dong Hoon OH, Yong Tae KWON, Jun Kyu LEE, Kyeong Rok SHIN, Yong Woon YEO
  • Publication number: 20210347749
    Abstract: The present invention relates to a novel p62 ligand compound, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for preventing or treating proteinopathies comprising the same as an active ingredient. The p62 ligand compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various proteinopathies by activating autophagy in cells and thus selectively eliminating in vivo proteins, organelles and aggregates.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 11, 2021
    Applicant: PROTECH Co., Ltd.
    Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao GANIPISETTI, Hee Yeon KIM, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
  • Publication number: 20210343656
    Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: November 4, 2021
    Applicant: Nepes Co., Ltd.
    Inventors: Yong Tae KWON, Jun Kyu Lee, Dong Hoon OH, Su Yun KIM, Kyeong Rok SHIN
  • Publication number: 20210299253
    Abstract: The present invention relates to a novel AUTOTAC chimeric compound in which a new p62 ligand and a target-binding ligand are connected by a linker, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for the prevention or treatment of diseases by degrading the target protein including the same as an active ingredient. They can target specific proteins to adjust their concentrations, and can also deliver drugs and other small molecule compounds to lysosomes. The AUTOTAC chimeric compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various diseases by selectively eliminating specific proteins.
    Type: Application
    Filed: July 24, 2019
    Publication date: September 30, 2021
    Applicant: PROTECH Co., Ltd.
    Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao GANIPISETTI, Hee Yeon KIM, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
  • Publication number: 20210288005
    Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 16, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Hyun Sik KIM, Seung Hwan SHIN, Yong Tae KWON, Dong Hoon SEO, Hee Cheol KIM, Dong Soo LEE
  • Publication number: 20210193602
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Jun Kyu LEE, Su Yun Kim, Dong Hoon OH, Yong Tae KWON, Ju Hyun NAM
  • Publication number: 20210163399
    Abstract: The present invention relates to a novel p62 ligand compound, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for preventing or treating misfolded protein diseases comprising the same as an active ingredient. The p62 ligand compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various proteinopathies by activating selective autophagy in cells and thus selectively eliminating in vivo proteins, organelles and aggregates.
    Type: Application
    Filed: July 24, 2019
    Publication date: June 3, 2021
    Applicant: PROTECH Co., Ltd.
    Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao Ganipisetti, Hee Yeon Kim, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
  • Patent number: 10964656
    Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 30, 2021
    Assignee: NEPES CO., LTD.
    Inventors: Yong Tae Kwon, Hee Cheol Kim, Seung Jun Moon, Jini Shim
  • Publication number: 20210024454
    Abstract: The present invention provides a compound represented by the following Chemical Formula 1 or a pharmaceutically acceptable salt thereof which can be effectively used for preventing or treating obesity or metabolic syndrome, and a pharmaceutical composition comprising the same. in Chemical Formula 1, R1 and R2 are the same as defined in the specification.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 28, 2021
    Applicant: PROTECH CO., LTD
    Inventors: Yong Tae KWON, Srinivasrao GANIPISETTI, Ki Woon SUNG, Eui Jung JUNG, Tae Hyun BAE, Su Ran MUN, Chan Hoon JUNG