Patents by Inventor Yong Tae Kwon
Yong Tae Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11450535Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.Type: GrantFiled: April 3, 2017Date of Patent: September 20, 2022Assignee: NEPES CO., LTD.Inventors: Yong-Tae Kwon, Jun-Kyu Lee, Si Woo Lim, Dong-Hoon Oh, Jun-Sung Ma, Tae-Won Kim
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Publication number: 20220278053Abstract: A technical idea of the present disclosure provides a semiconductor package, as a semiconductor package mounted on a circuit board, including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.Type: ApplicationFiled: March 24, 2020Publication date: September 1, 2022Applicant: NEPES CO., LTD.Inventors: Ju Hyun NAM, Jun Kyu LEE, Yong Tae KWON, Su Yun KIM, Dong Hoon OH
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Publication number: 20220165648Abstract: Disclosed is a semiconductor package including a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first surface of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second surface of the semiconductor chip; a conductive post disposed outside the semiconductor chip; a first redistribution structure, which is on the first surface of the semiconductor chip and includes a first redistribution insulation layer supporting the conductive stud and the conductive post; a second redistribution structure, which is on the second surface of the semiconductor chip and includes a second redistribution insulation layer disposed on the adhesive layer; and a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.Type: ApplicationFiled: November 11, 2021Publication date: May 26, 2022Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATIONInventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba
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Publication number: 20220148993Abstract: Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure.Type: ApplicationFiled: November 11, 2021Publication date: May 12, 2022Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATIONInventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba
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Publication number: 20210398869Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.Type: ApplicationFiled: October 17, 2019Publication date: December 23, 2021Applicant: NEPES CO., LTD.Inventors: Su Yun KIM, Dong Hoon OH, Yong Tae KWON, Jun Kyu LEE, Kyeong Rok SHIN, Yong Woon YEO
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Publication number: 20210347749Abstract: The present invention relates to a novel p62 ligand compound, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for preventing or treating proteinopathies comprising the same as an active ingredient. The p62 ligand compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various proteinopathies by activating autophagy in cells and thus selectively eliminating in vivo proteins, organelles and aggregates.Type: ApplicationFiled: July 24, 2019Publication date: November 11, 2021Applicant: PROTECH Co., Ltd.Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao GANIPISETTI, Hee Yeon KIM, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
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Publication number: 20210343656Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.Type: ApplicationFiled: September 26, 2019Publication date: November 4, 2021Applicant: Nepes Co., Ltd.Inventors: Yong Tae KWON, Jun Kyu Lee, Dong Hoon OH, Su Yun KIM, Kyeong Rok SHIN
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Publication number: 20210299253Abstract: The present invention relates to a novel AUTOTAC chimeric compound in which a new p62 ligand and a target-binding ligand are connected by a linker, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for the prevention or treatment of diseases by degrading the target protein including the same as an active ingredient. They can target specific proteins to adjust their concentrations, and can also deliver drugs and other small molecule compounds to lysosomes. The AUTOTAC chimeric compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various diseases by selectively eliminating specific proteins.Type: ApplicationFiled: July 24, 2019Publication date: September 30, 2021Applicant: PROTECH Co., Ltd.Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao GANIPISETTI, Hee Yeon KIM, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
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Publication number: 20210288005Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.Type: ApplicationFiled: February 19, 2021Publication date: September 16, 2021Applicant: Nepes CO., LTD.Inventors: Hyun Sik KIM, Seung Hwan SHIN, Yong Tae KWON, Dong Hoon SEO, Hee Cheol KIM, Dong Soo LEE
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Publication number: 20210193602Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.Type: ApplicationFiled: December 15, 2020Publication date: June 24, 2021Applicant: Nepes CO., LTD.Inventors: Jun Kyu LEE, Su Yun Kim, Dong Hoon OH, Yong Tae KWON, Ju Hyun NAM
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Publication number: 20210163399Abstract: The present invention relates to a novel p62 ligand compound, a stereoisomer, hydrate, solvate or prodrug thereof, and a pharmaceutical or food composition for preventing or treating misfolded protein diseases comprising the same as an active ingredient. The p62 ligand compound according to the present invention can be usefully used as a pharmaceutical composition for the prevention, amelioration or treatment of various proteinopathies by activating selective autophagy in cells and thus selectively eliminating in vivo proteins, organelles and aggregates.Type: ApplicationFiled: July 24, 2019Publication date: June 3, 2021Applicant: PROTECH Co., Ltd.Inventors: Yong Tae Kwon, Chang Hoon Ji, Srinivasrao Ganipisetti, Hee Yeon Kim, Su Ran Mun, Chan Hoon Jung, Eui Jung Jung, Ki Woon Sung
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Patent number: 10964656Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.Type: GrantFiled: May 30, 2019Date of Patent: March 30, 2021Assignee: NEPES CO., LTD.Inventors: Yong Tae Kwon, Hee Cheol Kim, Seung Jun Moon, Jini Shim
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Publication number: 20210024454Abstract: The present invention provides a compound represented by the following Chemical Formula 1 or a pharmaceutically acceptable salt thereof which can be effectively used for preventing or treating obesity or metabolic syndrome, and a pharmaceutical composition comprising the same. in Chemical Formula 1, R1 and R2 are the same as defined in the specification.Type: ApplicationFiled: March 26, 2019Publication date: January 28, 2021Applicant: PROTECH CO., LTDInventors: Yong Tae KWON, Srinivasrao GANIPISETTI, Ki Woon SUNG, Eui Jung JUNG, Tae Hyun BAE, Su Ran MUN, Chan Hoon JUNG
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Patent number: 10804146Abstract: A technical concept of the present disclosure provides a method of producing a semiconductor package, the method including operations of: arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.Type: GrantFiled: July 9, 2019Date of Patent: October 13, 2020Assignee: NEPES LAWEH CorporationInventors: Nam Chul Kim, Yong Woon Yeo, Yong Tae Kwon, Young Seok Lee
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Publication number: 20200273830Abstract: A semiconductor package according to an embodiment includes a semiconductor chip having a first surface in which a chip pad is formed, a first insulating layer arranged on the first surface of the semiconductor chip and including a first filler, a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer, a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer, a second insulating layer contacting the redistribution pattern on the first insulating layer and including a second filler, a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer, an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer, and an external connection terminal electrically connected to the UBM.Type: ApplicationFiled: February 17, 2020Publication date: August 27, 2020Applicant: Nepes Co., Ltd.Inventors: Yong Tae Kwon, Jun Kyu LEE, Kyeong Rok SHIN
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Publication number: 20190378807Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.Type: ApplicationFiled: May 30, 2019Publication date: December 12, 2019Inventors: Yong Tae KWON, Hee Cheol KIM, Seung Jun MOON, Jini SHIM
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Publication number: 20190333809Abstract: A technical concept of the present disclosure provides a method of producing a semiconductor package, the method including operations of: arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Applicant: NEPES CO., LTD.Inventors: Nam Chul Kim, Yong Woon Yeo, Yong Tae Kwon, Young Seok Lee
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Patent number: 10391067Abstract: The pharmacokinetics and key technologies of the present invention are summarized in FIG. 1. Particularly, malignant misfolded proteins such as mutant huntingtin and alpha-synuclein are coagulated and grow into oligomeric coagulum ({circle around (1)}, {circle around (2)}, fibrillar coagulum ({circle around (3)}) and eventually inclusion body ({circle around (4)}). Young neurons produce a large amount of Nt-Arg through N-terminal arginylation ({circle around (5)}) of vesicle chaperones such as BiP secreted into the cytoplasm, and then arginylated BiP (R-BiP) is secreted binds to the misfolded proteins ({circle around (6)}). As a ligand, the Nt-Arg of R-BiP binds to the p62 ZZ domain ({circle around (7)}), and the normally inactivated closed form of p62 is changed to an open form, leading to structural activation ({circle around (8)}). As a result, PB1 and LC3-binding domains are exposed.Type: GrantFiled: July 15, 2016Date of Patent: August 27, 2019Assignee: AUTOTAC BIOInventors: Yong Tae Kwon, Bo Yeon Kim, Hyunjoo Cha, Young Dong Yoo, Ji-eun Yu
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Publication number: 20190122899Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.Type: ApplicationFiled: April 3, 2017Publication date: April 25, 2019Applicant: NEPES CO., LTD.Inventors: Yong-Tae KWON, Jun-Kyu LEE, Si Woo LIM, Dong Hoon OH, Jun Sung MA, Tae-Won KIM
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Publication number: 20180243244Abstract: The pharmacokinetics and key technologies of the present invention are summarized in FIG. 1. Particularly, malignant misfolded proteins such as mutant huntingtin and alpha-synuclein are coagulated and grow into oligomeric coagulum ({circle around (1)}, {circle around (2)}, fibrillar coagulum ({circle around (3)}) and eventually inclusion body ({circle around (4)}). Young neurons produce a large amount of Nt-Arg through N-terminal arginylation ({circle around (5)}) of vesicle chaperones such as BiP secreted into the cytoplasm, and then arginylated BiP (R-BiP) is secreted binds to the misfolded proteins ({circle around (6)}). As a ligand, the Nt-Arg of R-BiP binds to the p62 ZZ domain ({circle around (7)}), and the normally inactivated closed form of p62 is changed to an open form, leading to structural activation ({circle around (8)}). As a result, PB1 and LC3-binding domains are exposed.Type: ApplicationFiled: July 15, 2016Publication date: August 30, 2018Inventors: Yong Tae Kwon, Bo Yeon Kim, Hyunjoo Cha, Young Dong Yoo, Ji-eun Yu