Abstract: Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.

Abstract: Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.

Abstract: In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

Abstract: In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

Abstract: A semiconductor package substrate is provided. The package substrate includes a mold base and an interposer block embedded in the mold base, said interposer block having a plurality of vertical conductive lines therein. A metallization layer is formed on the surface of the interposer block or the mold base, said metallization layer being electrically connected to at least one of the vertical conductive lines. A semiconductor chip may be mounted on or embedded in the mold base.

Abstract: A semiconductor package is provided. The package includes a package substrate with a first surface and a second surface on the opposite side, and a plurality of via sets connecting vertically the first surface with the second surface, said via sets having a plurality of micro vias and filled with conductive material. The micro vias are grouped together, and the distance between micro vias in the via set is smaller than the distance between neighboring via sets.

Abstract: The invention provides methods and compositions for modulating angiogenesis in a subject. The methods of modulating angiogenesis in a subject include administering to the subject a modulator of N-terminal arginylation activity. The invention also provides a method of identifying such a modulator and a method of in vitro screening for modulators of N-terminal arginylation activity. Additionally, the invention provides a method of treating an angiogenesis-related disorder.

Abstract: Screening assays that allow for the identification of agents that modulate the activity of the arginylation branch of the N-end rule pathway are provided. Also provided are method of using an agent that modulate the activity of the arginylation branch of the N-end rule pathway to increase or decrease protein degradation in a cell, and to modulate physiologic and pathologic associated with N-end rule pathway mediated arginylation.

Abstract: This invention is about a bag for a pet. It has fluid acceptation space which is suitable for physical character of a pet. Also it makes a pet safe and a man easy to walk as wearing more closer to his body. It consist of a main body which of space made bottom gradient to body direction from the front of be in pet's head, a form frame which set a pair with a flexible cushion on open surface and get smaller in diameter, and a changeable length shoulder strap which link both of a main body.

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a in centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality in of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: The invention provides methods and compositions for modulating angiogenesis in a subject. The methods of modulating angiogenesis in a subject include administering to the subject a modulator of N-terminal cysteine oxygenase activity. The invention also provides a method of identifying such a modulator and a method of in vitro screening for modulators of N-terminal cysteine oxygenase activity. Additionally, the invention provides a method of treating an angiogenesis-related disorder.

Abstract: The invention provides methods and compositions for modulating angiogenesis in a subject. The methods of modulating angiogenesis in a subject include administering to the subject a modulator of N-terminal arginylation activity. The invention also provides a method of identifying such a modulator and a method of in vitro screening for modulators of N-terminal arginylation activity. Additionally, the invention provides a method of treating an angiogenesis-related disorder.

Abstract: A chip size package is fabricated by: etching portions of a copper film on an insulating film tape, forming a solder mask on the insulating film tape excluding inner holes of metal pattern units and four edge portions of the copper film, electroplating, attaching the semiconductor chip, sealing the semiconductor chip with an epoxy, etching to expose the chip pads, electrically connecting the chip pads by wires, eliminating portions of the copper film remaining at the four edge portions and cutting the insulating film tape into individual units.

Abstract: A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound;

Abstract: A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound;

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: Disclosed here is a nucleic acid sequence encoding a recognition component of the N-end rule pathway. This nucleic acid sequence is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 1 under stringent hybridization conditions. Such conditions are defined below. Also disclosed is a nucleic acid sequence encoding a recognition component of the N-end rule pathway which is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 2 under stringent hybridization conditions. Also disclosed are DNA expression vectors containing nucleic acid sequences of the type described above, as well as cells transformed with such expression vectors. Further disclosed are applications for the compositions described above.

Abstract: The present invention relates to a ball grid array (BGA) semiconductor package member and its manufacturing method employing a carrier frame and a substrate, and to a method of manufacturing a BGA semiconductor package using the BGA semiconductor package member. In manufacturing the conventional BGA semiconductor package, conventional package manufacturing equipment cannot be employed because a boat is used during processing which requires additional equipment, and thus increases the costs of production. However, a BGA semiconductor package manufacturing method employing a carrier frame and substrate according to the present invention is compatible with conventional semiconductor package manufacturing equipment.

Abstract: Disclosed here is a nucleic acid sequence encoding a recognition component of the N-end rule pathway. This nucleic acid sequence is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 1 under stringent hybridization conditions. Such conditions are defined below. Also disclosed is a nucleic acid sequence encoding a recognition component of the N-end rule pathway which is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 2 under stringent hybridization conditions. Also disclosed are DNA expression vectors containing nucleic acid sequences of the type described above, as well as cells transformed with such expression vectors. Further disclosed are applications for the compositions described above.