Abstract: A chip size package is fabricated by: etching portions of a copper film on an insulating film tape, forming a solder mask on the insulating film tape excluding inner holes of metal pattern units and four edge portions of the copper film, electroplating, attaching the semiconductor chip, sealing the semiconductor chip with an epoxy, etching to expose the chip pads, electrically connecting the chip pads by wires, eliminating portions of the copper film remaining at the four edge portions and cutting the insulating film tape into individual units.

Abstract: A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound;

Abstract: A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound;

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: Disclosed here is a nucleic acid sequence encoding a recognition component of the N-end rule pathway. This nucleic acid sequence is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 1 under stringent hybridization conditions. Such conditions are defined below. Also disclosed is a nucleic acid sequence encoding a recognition component of the N-end rule pathway which is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 2 under stringent hybridization conditions. Also disclosed are DNA expression vectors containing nucleic acid sequences of the type described above, as well as cells transformed with such expression vectors. Further disclosed are applications for the compositions described above.

Abstract: The present invention relates to a ball grid array (BGA) semiconductor package member and its manufacturing method employing a carrier frame and a substrate, and to a method of manufacturing a BGA semiconductor package using the BGA semiconductor package member. In manufacturing the conventional BGA semiconductor package, conventional package manufacturing equipment cannot be employed because a boat is used during processing which requires additional equipment, and thus increases the costs of production. However, a BGA semiconductor package manufacturing method employing a carrier frame and substrate according to the present invention is compatible with conventional semiconductor package manufacturing equipment.

Abstract: Disclosed here is a nucleic acid sequence encoding a recognition component of the N-end rule pathway. This nucleic acid sequence is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 1 under stringent hybridization conditions. Such conditions are defined below. Also disclosed is a nucleic acid sequence encoding a recognition component of the N-end rule pathway which is characterized by the ability to specifically hybridize to the nucleic acid sequence of SEQ ID NO 2 under stringent hybridization conditions. Also disclosed are DNA expression vectors containing nucleic acid sequences of the type described above, as well as cells transformed with such expression vectors. Further disclosed are applications for the compositions described above.