Abstract: The present invention provides a method and apparatus for fast 3D ultrasound imaging. The method comprises data acquisition, desired data selection, data smoothing, table construction, ray casting, table look-up, ray synthesis and final result output. The apparatus comprises an acquisition module, a selection module, a smoothing module, a construction module, a ray casting module, a table look-up module, a synthesis module and an output module. The present invention can avoid a huge amount of unnecessary reconstruction calculations by smoothing preprocessing and constructing the reconstruction table and the gradient table as well as transforming coordinates of the points where necessary. The present invention has greater practical applicability, because the existing imaging technology demands that the radius for rotating the probe be identical to the radius of the probe.

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.

Abstract: The present invention provides a method and module for preprocessing ultrasound imaging. The method comprises a calculation step for constructing a multivalue vector field and a smoothing step for smoothing the whole volume data. The method further comprises a judgement step and minification and magnification steps. The module includes a calculation unit, a smoothing unit, a judgement unit, a minification unit and a magnification unit. According to the method for preprocessing ultrasound imaging, speckle noise can be eliminated effectively by calculating a mean value of a plurality of nodes distributed over the surface, so as to implement the smoothing. Therefore, this method is capable of smoothing data without compromising details.

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.

Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

Abstract: Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.

Abstract: A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.

Abstract: Good quality fusion splicing of optical fibers with very different melting points (even 800° C. and 1800° C.) can be achieved by heating the end (3) of the fiber of lower melting point to a substantial extent (preferably entirely) by conduction from the pre-heated end (4) of the fiber of higher melting point. Preheating is suitably by a laser with its beam (15) centered close to the interface between the two fibers (or slightly displaced in the direction of the fiber of higher melting point if the intensity of the beam is relatively evenly spread) using a screen (13) to shade the fiber of lower melting point from the beam.

Abstract: Wireless, hands-free Internet access is facilitated using a mobile unit including a text-to-speech converter and a speech recognition unit. A processing unit operating in conjunction with a cellular telephone and a personal information management unit runs voice-clipping applications whose resources include markup language based information exchanged wirelessly, such that the processing unit interacts with a content server connected to the Internet. Hands-free access to the Internet is thereby gained.

Abstract: Good quality fusion splicing of optical fibers with very different melting points (even 800° C. and 1800° C.) can be achieved by heating the end (3) of the fiber of lower melting point to a substantial extent (preferably entirely) by conduction from the pre-heated end (4) of the fiber of higher melting point.

Abstract: A method and apparatus for aligning optical fibers for splicing utilizing a grooved holder (22) and positioning arms that engage the fiber ends (17, 18) and bring them precisely together in alignment for splicing. The grooves (24, 24′, 26, 26′, 28, 28′) of the holder have a channel (27) extending therebetween. The precisely formed grooves (24, 24′, 26, 26′, 28, 28′) provide X and Y alignment of the fibers in conduction with positioning arms (32, 32′) having resilient pads (36, 36′). The resilient pads (36, 36′) allow the positioning arms (32, 32′) to frictionally engage the optical fibers (15, 16) and bring their respective ends (17, 18) into position for fusion splicing.

Abstract: An automated optical chip holder for use in a pigtailing system precisely positions an optical chip at a predetermined location in three-dimensional space to align the optical chip within the pigtailing system. An adjustable chuck assembly is driven by a stepper motor under PLC control to position optical chip. After alignment, the optical chip is clamped by the adjustable chuck assembly during the pigtailing process to prevent the optical chip from moving out of alignment. This significantly reduces the occurrence of glue-joint failure and misalignment due to retraction stress. The clamp is fabricated using soft resilient materials at the point of contact with the chip. Thus, uniform pressure is exerted on the chip, micro-vibrations are absorbed, damage to the chip is reduced, and the necessity of precision motion control of the chuck assembly is avoided.