Abstract: Sulfur sensors are formed by coating a conductive substrate with ZnO microstructures that are reactive with sulfur in liquids, such as fuel, using MOCVD. The ZnO is changed to ZnS over time and causes the voltage across the sensors to change under a constant current by at least about 25%. The time required for such saturation to occur can then be correlated to a sulfur concentration in the liquid.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract: A browser-enabled device includes a browser-based user interface and control architecture, which has a browser core, a browser framework, and a user interface. The user interface is written using a markup language. In processing event registrations, the browser framework receives an event registration. The received event registration having a response unique resource identifier (URI) content and a priority field. The priority field of the received event registration is examined to determine priority of the received event registration. If the browser core is loading the response URI content of a prior event registration and if the priority of the received event registration is higher than the priority of the prior event registration, then the loading of the response URI content of the prior event registration is halted, and loading of the response URI content of the received event registration is begun.

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract: The Field Testing Instrument (FTI) is designed for use in the regular maintenance and installation of airport Precision Approach Path Indicator (PAPI). The FTI is a self-contained and portable instrument that accurately measures the most important PAPI parameters, such as vertical aiming angle, transition angle, and light intensity. In addition to working with the current incandescent PAPIs, the FTI also measures parameters specific to the next generation LED PAPI. The FTI uses modern, efficient technology to reduce the life-cycle cost of approach lighting systems. The FTI improves on traditional PAPI testing methods by directly measuring the PAPI light beam focused to a target plate, as if seen from the pilot perspective. Due to significantly improvements in measurement accuracy and reliability, the FTI may supplement and even replace costly flight checks for PAPI maintenance with ground based operation.

Abstract: An LED based omni-directional light engine includes a toroidal lens coupled to a controller circuit board and two or more evenly spaced LEDs mounted to the controller circuit board. The toroidal lens includes an inner surface coated with a layer of reflection materials, an outer surface, and a flat base surface. The controller circuit board is electrically coupled to a power source. The LEDs are located immediately under the flat base surface. The inner surface substantially reflects light beams emitted from the LEDs to the outer surface which refracts the beams to the omni-directions.

Abstract: A precision approach path indicator system (PAPI) including multiple LHA indicators and power sources. Each LHA indicator comprises several assembly modules, with each module made up of several red and white LEDs, several collimating lens, one optical combiner, and one projection lens set. From a side view of the module, the red LEDs are placed on top of white LEDs, with a collimating lens in front of each LED. The optical combiner is in front of both the red and white LEDs, slightly above the white LEDs in vertical placement. The optical combiner has a reflective coating on the bottom surface, and a red light filter coating on the projection surface. The combined beam of light is projected out through a projection lens at front of the assembly module.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.

Abstract: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.

Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.

Abstract: A browser-enabled device includes a browser-based user interface and control architecture, which has a browser core, a browser framework, and a user interface. The user interface is written using a markup language. In processing event registrations, the browser framework receives an event registration. The received event registration having a response unique resource identifier (URI) content and a priority field. The priority field of the received event registration is examined to determine priority of the received event registration. If the browser core is loading the response URI content of a prior event registration and if the priority of the received event registration is higher than the priority of the prior event registration, then the loading of the response URI content of the prior event registration is halted, and loading of the response URI content of the received event registration is begun.

Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.

Abstract: The invention provides a method and apparatus for fast volume rendering of 3D ultrasound image, comprising a dividing step, a calculating step, a determining step, a morphological closing operation step and a filling step, wherein each flat grid can be entirely filled by obtaining gray-scale values for all pixels inside the grid through interpolating; for the non-flat grid, the steps of dividing, calculating, determining and filling are performed repeatedly until the non-flat grid is subdivided into atomic grids to calculate gray-scale values for remaining pixels by projection. As the method can be finished in the rear end, no difficulty occurs in the implementation, and no process for being adapted to previous frames is required. Therefore, the method can improve the rendering speed effectively without degrading the quality of image to put 3D ultrasound imaging to the best use.