Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A device for controlling the level of a transmission signal according to the channel loading is provided. The device may include a plurality of semiconductor devices and a controller to control the plurality of semiconductor devices. The controller may control the level of a signal to be transmitted to each of the plurality of semiconductor devices according to the channel loading on each semiconductor device.

Abstract: A source driver for display devices includes line pair driving blocks. Each of the line pair driving blocks includes a de-multiplexing portion for de-multiplexing first and second digital data to generate first and second de-multiplexing data, a decoding portion for decoding the first and second de-multiplexing data to generate first and second analog data, and a multiplexing portion for multiplexing the first and second analog data to generate first and second gradation voltages. In the source driver, the de-multiplexing portion is controlled by signals having information of loading timing for the digital data and information of polarity for the gradation voltages.

Abstract: An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.

Abstract: A differential data transferring system and method uses three level voltages to simultaneously transfer three signals (for example, two data signals and one clock signal) across two transfer line sets (i.e., four transfer lines). Therefore, the differential data transferring method increases transferring efficiency by using fewer transfer lines. Also, according to the differential data transferring system and method, one of two transfer lines forming a transfer line set is controlled to a middle voltage level, while the other transfer line is controlled to either a high voltage or a low voltage. Accordingly, the voltage difference between the two transfer lines may be maintained at a constant amplitude. Additionally, the difference between first and second dividing voltages DC1 and DC2, which are used for generating a reference output data, is controlled to maintain a constant amplitude. Therefore, the differential data transferring system and method may provide improved operation reliability.

Abstract: A device for controlling the level of a transmission signal according to the channel loading is provided. The device may include a plurality of semiconductor devices and a controller to control the plurality of semiconductor devices. The controller may control the level of a signal to be transmitted to each of the plurality of semiconductor devices according to the channel loading on each semiconductor device.

Abstract: Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).

Abstract: A device for controlling the level of a transmission signal according to the channel loading is provided. The device may include a plurality of semiconductor devices and a controller to control the plurality of semiconductor devices. The controller may control the level of a signal to be transmitted to each of the plurality of semiconductor devices according to the channel loading on each semiconductor device.

Abstract: An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A differential data transferring system and method uses three level voltages to simultaneously transfer three signals (for example, two data signals and one clock signal) across two transfer line sets (i.e., four transfer lines). Therefore, the differential data transferring method increases transferring efficiency by using fewer transfer lines. Also, according to the differential data transferring system and method, one of two transfer lines forming a transfer line set is controlled to a middle voltage level, while the other transfer line is controlled to either a high voltage or a low voltage. Accordingly, the voltage difference between the two transfer lines may be maintained at a constant amplitude. Additionally, the difference between first and second dividing voltages DC1 and DC2, which are used for generating a reference output data, is controlled to maintain a constant amplitude. Therefore, the differential data transferring system and method may provide improved operation reliability.

Abstract: A source driver for display devices includes line pair driving blocks. Each of the line pair driving blocks includes a de-multiplexing portion for de-multiplexing first and second digital data to generate first and second de-multiplexing data, a decoding portion for decoding the first and second de-multiplexing data to generate first and second analog data, and a multiplexing portion for multiplexing the first and second analog data to generate first and second gradation voltages. In the source driver, the de-multiplexing portion is controlled by signals having information of loading timing for the digital data and information of polarity for the gradation voltages.

Abstract: A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.

Abstract: For generating source line voltages in a display device, gray scale data is received at a source driver for a first sub-pixel of a pixel. The source driver generates a first source line voltage for the first sub-pixel and a second source line voltage for a second sub-pixel from the gray scale data of the first sub-pixel. Thus, data transfer rate and/or data buses are minimized for in turn minimizing power consumption and EMI (electromagnetic interference).

Abstract: A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage.

Abstract: Provided is a current-mode semiconductor integrated circuit device that operates in a voltage mode during a test mode. The current-mode semiconductor integrated circuit device includes a first transmitting converter, a first receiving converter, a second transmitting converter, and a second receiving converter. During the test mode, one of a first signal path and a second signal path is selected according to the location of the chip. In the first signal path, the first transmitting converter, the first receiving converter, and the second transmitting converter operate. In the second signal path, the second transmitting converter, the second receiving converter, and the first transmitting converter operate. Each of the first and second transmitting converters receives a test voltage signal and converts it into a current signal. Each of the first and second receiving converters generates a reference voltage signal, compares it with the test voltage signal, and outputs the comparing result.

Abstract: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.