Abstract: A gamma signal supplying apparatus includes a timing controller for storing predetermined gamma values as digital values, and for transmitting one of the digital values serially. The gamma supplying apparatus may further include a gamma digital-to-analog controller (DAC) for receiving the serial digital gamma value, and for converting the serial digital gamma value into a first analog gamma value, and a plurality of column drive units, each of the plurality of column drive units for generating a second analog gamma value, for comparing the second analog gamma value to the first analog gamma value, and for outputting a gray level value based on the second analog gamma value if both values are substantially identical.

Abstract: A method for controlling a memory cell capable of extending a refresh interval and lengthening a storing time of a cell data by raising a data of a high level voltage stored in the cell capacitor above Vdd, thereby reducing power consumption.

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers invert the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Abstract: A circuit for generating equalization pulses for a memory device is disclosed, which prevents formation of a short circuit between a Vdd potential and a Vss potential when two address transition signals are successively generated, and which generates the equalization pulses by using address transition pulses and by reducing the access time of the memory device. The equalization pulse generating circuit includes a NAND circuit section for outputting a NAND logic of address transition signals under address transitions to an equalization pulse generating node, a delay circuit section for delaying an output of the equalization pulse generating node for a certain period of time, so as to generate at least one delayed output signal, and a maintaining circuit section for logically processing the delayed output signal of the delay circuit section and the NAND logic output of the NAND circuit section, so as to maintain the state of the equalization pulse generating node in the same state for a certain period of time.

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers inverters the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Abstract: An address transition detection circuit for driving an internal circuit of a memory device, includes an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal, a latch circuit for generating first and second latch signals, a feedback circuit for generating a feedback signal, first and second delay circuits for generating first and second delay signals by delaying the first and second latch signals for a prescribed delay time, and an address transition detection signal output circuit for receiving the first and second latch signals and the first and second delay signals, and generating an address transition detection signal having a pulse width longer than at least the twice the prescribed delay time of the first or second delay circuit when the address signal changes, thereby preventing malfunction of the memory device.

Abstract: A multi-bit testing circuit for testing a semiconductor memory device having a plurality of memory cells.