Patents by Inventor Yong-weon Jeon

Yong-weon Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060158420
    Abstract: For generating source line voltages in a display device, gray scale data is received at a source driver for a first sub-pixel of a pixel. The source driver generates a first source line voltage for the first sub-pixel and a second source line voltage for a second sub-pixel from the gray scale data of the first sub-pixel. Thus, data transfer rate and/or data buses are minimized for in turn minimizing power consumption and EMI (electromagnetic interference).
    Type: Application
    Filed: August 22, 2005
    Publication date: July 20, 2006
    Inventors: Il-Kwon Chang, Yong-Weon Jeon
  • Patent number: 7075352
    Abstract: There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n?1)th unit cell and a signal output from an (n+1 )th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: July 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Kyung Kim, Yong-Weon Jeon
  • Publication number: 20060139084
    Abstract: There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n?1)th unit cell and a signal output from an (n+1)th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.
    Type: Application
    Filed: February 28, 2006
    Publication date: June 29, 2006
    Inventors: Do-Kyung Kim, Yong-Weon Jeon
  • Publication number: 20060133539
    Abstract: A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and cascode-increased output impedance. In addition, a signal converter generates an output signal indicating a difference between the buffered data current and a reference current. The reference current may also be received and buffered by a regulated cascode buffer with cascode-reduced input impedance and cascode-increased output impedance.
    Type: Application
    Filed: September 9, 2005
    Publication date: June 22, 2006
    Inventors: Il-Kwon Chang, Yong-Weon Jeon
  • Publication number: 20060125671
    Abstract: A source driving circuit for a display device may include a first latch configured to store first video data corresponding to a first horizontal line and a second latch configured to store second video data corresponding to a second horizontal line following the first horizontal line. The first and second latches may alternately store video data of different horizontal lines. The source driving circuit may further include a digital-to-analog converter (DAC) configured to convert the stored first and second video data into analog signals, a first sample-and-hold circuit configured to sample and store an output signal of the DAC, a second sample-and-hold circuit configured to sample and store an output signal of the first sample-and-hold circuit, and an output switch configured to provide an output signal of the second sample-and-hold circuits to the display panel.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 15, 2006
    Inventors: Il-Kwon Chang, Yong-Weon Jeon
  • Publication number: 20060119739
    Abstract: A gamma correction apparatus and methods thereof. The gamma correction apparatus may include at least one switching unit and a digital-to-analog converter, for example a capacitor digital-to-analog converter. The switching unit may transfer a first voltage to the digital-to-analog converter in response to a control signal. The digital-to-analog converter may generate a plurality of linear lines based at least in part on the first voltage to approximate a non-linear curve by generating a voltage transmission characteristic curve. A received digital signal may be converted into an analog signal based on the generated voltage transmission characteristic curve.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 8, 2006
    Inventors: Il-kwon Chang, Yong-weon Jeon
  • Publication number: 20060114217
    Abstract: A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.
    Type: Application
    Filed: September 30, 2005
    Publication date: June 1, 2006
    Inventors: Kyung-Wol Kim, Yong-Weon Jeon
  • Publication number: 20050179500
    Abstract: A regulated cascode amplifier includes a main cascode amplifier and a feed-back amplifier. The main cascode amplifier has an input transistor coupled in a stack with an output transistor at an input control node. The feed-back amplifier including a plurality of transistors with gates of the transistors being coupled together to the input control node and with drains of the transistors being coupled together at a gate of the output transistor. The transistors of the feed-back amplifier are biased from connections to the main cascode amplifier for smaller chip area.
    Type: Application
    Filed: February 7, 2005
    Publication date: August 18, 2005
    Inventors: Il-Kwon Chang, Yong-Weon Jeon
  • Patent number: 6930518
    Abstract: A level shifter changes an input signal whose level changes between a first voltage level and a ground voltage level into an output signal whose level changes between a second voltage level and the ground voltage level. The level shifter comprising a first input transistor and a second input transistor which receive the input signal and an inversion signal of the input signal, respectively; a first load transistor and a second load transistor, one side of each transistor being connected to the second voltage level; a first switch transistor connected between the first load transistor and the first input transistor, responding to the inversion signal; a second switch transistor connected between the second load transistor and the second input transistor, responding to the input signal; a first output unit for generating an output signal; and a second output unit that generates a complementary signal of the output signal.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Kyung-Wol Kim, Yong-Weon Jeon
  • Publication number: 20050174147
    Abstract: A current mode transmitter includes a first sink current path, through which a current flows from an output port according to a first bias voltage, a charge error canceller, which supplies a current from a high power supply voltage to a current control port in response to an input signal and counteracts a variation of a second bias voltage in response to an inverted input signal, which has an opposite polarity to that of the input signal, and the second bias voltage, and a second sink current path, which sinks current supplied from the output port in response to the second bias voltage and the inverted input signal, the second sink current path being controlled by the current control port. The input signal and the inverted input signal are complementary.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 11, 2005
    Inventors: Il-kwon Chang, Yong-weon Jeon
  • Patent number: 6927609
    Abstract: A current-mode data receiving device with sufficient fidelity for a display system. The receiving device includes: a current mirror, where an input current signal and a feedback current signal is received at a first terminal thereof and an output current signal with a current magnitude proportional to (e.g., equal to) the sum of the magnitudes of the input current signal and of the feedback current signal is output through a second terminal thereof; and a feedback unit that uses the magnitude of the output current signal as feedback to determined the magnitude and direction of the feedback current to the first terminal, and causes a decreases in the magnitude of the output current signal by a predetermined amount if the output current signal is at a high level, and increases the current magnitude of the output current signal by the predetermined amount if the magnitude of the output current signal is at a low level.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 9, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-kwon Chang, Yong-weon Jeon, Ji-woon Jung
  • Publication number: 20050162204
    Abstract: Provided are a delay locked loop (DLL) using an oscillator and a counter and a clock synchronizing method. The DLL converts cycle information of an input clock signal into digital information using the oscillator and the counter and generates output clock signals from the input clock signal using the digital information after a predetermined delay time elapses. The output clock signals each have a duty cycle of 50%.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 28, 2005
    Inventors: Jang-Sub Lee, Yong-Weon Jeon
  • Publication number: 20050162374
    Abstract: A thin film transistor liquid crystal display (TFT-LCD) source driver for implementing a self burn-in test and a self burn-in test method are provided. The TFT-LCD source driver includes a self burn-in signal generator that generates a self burn-in signal and a burn-in load signal, a burn-in data generator that generates a burn-in data signal and a burn-in polarity control signal in response to the self burn-in signal and a clock signal. The TFT-LCD source driver also includes first and second switching units. The first switching unit transmits the burn-in load signal as an internal load signal, transmits the burn-in data signal as an internal digital data signal, and transmits the burn-in polarity control signal as an internal polarity control signal, in response to activation of the self burn-in signal. The second switching unit transmits outputs of output drivers to all channels of the TFT-LCD source driver in response to the internal load signal.
    Type: Application
    Filed: December 21, 2004
    Publication date: July 28, 2005
    Inventors: Kyung-Wol Kim, Yong-Weon Jeon
  • Publication number: 20050152189
    Abstract: A display device includes source drivers connected to a timing controller in a serial cascade. First through third buses are connected between the timing controller and a first source driver of source drivers. In a first period of time, a clock signal is transmitted via the first bus, a first operation control signal is transmitted via the second bus, a second operation control signal is transmitted via the third bus, and a polarity control signal is transmitted via the third bus. In a second period of time, the clock signal is transmitted via the first bus, the first operation control signal is transmitted via the second bus, and the second operation control signal is transmitted via the third bus. Source drivers generate a data initiation signal and a load signal using a combination of the logic levels of the operation control signals during each period.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 14, 2005
    Inventors: Kyung-Wol Kim, Yong-Weon Jeon
  • Patent number: 6798368
    Abstract: A gamma signal supplying apparatus includes a timing controller for storing predetermined gamma values as digital values, and for transmitting one of the digital values serially. The gamma supplying apparatus may further include a gamma digital-to-analog controller (DAC) for receiving the serial digital gamma value, and for converting the serial digital gamma value into a first analog gamma value, and a plurality of column drive units, each of the plurality of column drive units for generating a second analog gamma value, for comparing the second analog gamma value to the first analog gamma value, and for outputting a gray level value based on the second analog gamma value if both values are substantially identical.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: September 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Woon Jung, Yong-Weon Jeon
  • Publication number: 20040178976
    Abstract: The invention, in part, provides a method of (and corresponding apparatus for) receiving (and similarly transmitting) data signals over data lines. Such a method of receiving comprises: organizing said data lines into groups, each group having N input data signals and M reference signals, wherein N is a non-zero, positive integer; associating M reference signals on M reference lines with each group of N input data lines, wherein M is a non-zero, positive integer and N>M; and receiving data on said data lines and reference signals on said reference lines; and determining, for each group, data values on said data lines according to differences between signal parameters on said N data lines and signal parameters on said M reference lines, respectively.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Inventors: Yong Weon Jeon, Chang Sig Kang
  • Publication number: 20040174194
    Abstract: A current-mode data receiving device with sufficient fidelity for a display system. The receiving device includes: a current mirror, where an input current signal and a feedback current signal is received at a first terminal thereof and an output current signal with a current magnitude proportional to (e.g., equal to) the sum of the magnitudes of the input current signal and of the feedback current signal is output through a second terminal thereof; and a feedback unit that uses the magnitude of the output current signal as feedback to determined the magnitude and direction of the feedback current to the first terminal, and causes a decreases in the magnitude of the output current signal by a predetermined amount if the output current signal is at a high level, and increases the current magnitude of the output current signal by the predetermined amount if the magnitude of the output current signal is at a low level.
    Type: Application
    Filed: February 11, 2004
    Publication date: September 9, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Il-kwon Chang, Yong-weon Jeon, Ji-woon Jung
  • Publication number: 20040164941
    Abstract: A liquid crystal display (LCD) source driving circuit having a reduced circuit footprint. A plurality of the LCD source driving circuits are typically disposed along a side of an LCD panel and drives the LCD panel in response to digital image signals, such as color signals R, G, B, and control signals received from a control circuit. Also, the LCD source driving circuit includes a plurality of latch circuits, a plurality of level shifters, a plurality of Positive voltage digital-to-analog decoders, a plurality of Negative voltage digital-to-analog decoders, a plurality of multiplexor (MUX) circuits, and a plurality of amplifiers. Thus, the LCD source driving circuit is capable of selectively latching digital image signals using the latch circuits with MUX circuit functions, thereby reducing the circuit footprint of source vertical channels within the LCD source driving circuit.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 26, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do-Kyung Kim, Yong-Weon Jeon
  • Publication number: 20040160262
    Abstract: A level shifter changes an input signal whose level changes between a first voltage level and a ground voltage level into an output signal whose level changes between a second voltage level and the ground voltage level. The level shifter comprising a first input transistor and a second input transistor which receive the input signal and an inversion signal of the input signal, respectively; a first load transistor and a second load transistor, one side of each transistor being connected to the second voltage level; a first switch transistor connected between the first load transistor and the first input transistor, responding to the inversion signal; a second switch transistor connected between the second load transistor and the second input transistor, responding to the input signal; a first output unit for generating an output signal; and a second output unit that generates a complementary signal of the output signal.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Kyung-Wol Kim, Yong-Weon Jeon
  • Publication number: 20040160257
    Abstract: There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n−1)th unit cell and a signal output from an (n+1 )th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 19, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do-Kyung Kim, Yong-Weon Jeon