Abstract: A vertical MOSFET is provided in an output stage region of a semiconductor substrate while a lateral n-channel MOSFET and a vertical diode are provided in a circuit region. The vertical diode is constituted by a p+-type diffusion region that penetrates a p?-type well region in a depth direction. A bottom of a first contact trench provided in an n+-type source region of the vertical MOSFET is covered by a p++-type contact region. A bottom of a second contact trench provided in an n+-type source region of the lateral n-channel MOSFET is covered by a p++-type contact region and a third contact trench provided in an n+-type drain region is covered entirely by the n+-type drain region.

Abstract: A method of manufacturing a semiconductor integrated circuit, includes: forming a first well region having a second conductivity type in an upper portion of a support layer having a first conductivity type; forming an oxide film on the first well region by a thermal oxidation method to decrease a concentration of impurities at an top surface of top surface side of the first well region; removing the oxide film; forming a second well region having the first conductivity type in an upper portion of the first well region; and merging a semiconductor element having a main electrode region having the second conductivity type in the second well region.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A p+-type anode region that forms a contact of an anode electrode on a front surface of a semiconductor substrate and a p+-type starting substrate of a rear surface of the semiconductor substrate is formed on the front surface of the semiconductor substrate, whereby an up-anode type vertical diode is configured. The semiconductor substrate has a p?-type epitaxial layer stacked on the p+-type starting substrate, and a p-type transition layer in a surface layer of the p?-type epitaxial layer, facing the p+-type starting substrate. A p-type anode diffusion region is provided between a p+-type surface anode region and the p-type transition layer, and contacts the p+-type surface anode region and the p-type transition layer. A p-type impurity concentration of the p-type anode diffusion region decreases from an interface with the p+-type surface anode region toward an interface with the p-type transition layer.

Abstract: A vertical MOSFET is provided in an output stage region of a semiconductor substrate while a lateral n-channel MOSFET and a vertical diode are provided in a circuit region. The vertical diode is constituted by a p+-type diffusion region that penetrates a p?-type well region in a depth direction. A bottom of a first contact trench provided in an n+-type source region of the vertical MOSFET is covered by a p++-type contact region. A bottom of a second contact trench provided in an n+-type source region of the lateral n-channel MOSFET is covered by a p++-type contact region and a third contact trench provided in an n+-type drain region is covered entirely by the n+-type drain region.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A semiconductor device includes a lateral MOSFET and a vertical semiconductor device that are formed on the same semiconductor substrate. In the lateral MOSFET, the voltage of a back-gate electrode is set to be higher than the voltage of a source electrode and a gate electrode by greater than or equal to a prescribed value (greater than or equal to 40V). A drain-side diffusion region, a drain diffusion region, a drain electrode, a gate insulating film, a gate electrode, and a LOCOS film are formed in annular shapes centered on a source diffusion region. As a result, an active channel region between the drain diffusion region and the source diffusion region as well as peripheral portions of the LOCOS film are also annular-shaped.

Abstract: Current detection circuit of a semiconductor device provided with a shunt resistor, a voltage division ratio adjustment resistor and a selection circuit which selects a voltage division ratio of the latter and has enhancement type MOSFETs and Zener Zaps as trimming elements. One of the Zener Zaps is trimmed and a divided voltage of the voltage division ratio adjustment resistor connected in parallel with the shunt resistor is outputted. The detected voltage in which variation of the resistance of the shunt resistor has been cancelled is therefore outputted. As the shunt resistor and the voltage division ratio adjustment resistor are laminated together, it is possible to obtain a current detection circuit with a small area, which can detect a current flowing into a shunt resistor with high accuracy.

Abstract: A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate. A high concentration region is open in a normal time, but is short-circuited to a potential higher than that of a GND pad through a second wiring layer in a screening test time. Thus, a semiconductor device and a method for testing the semiconductor device are provided, in which a protection element can be prevented from breaking down and initial failure of a device which is formed on one and the same semiconductor substrate as the protection element can be detected accurately.

Abstract: An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

Abstract: A horizontal MOSFET is arranged in parallel to a horizontal MOSFET and a portion of a return current IL which flows to a linear solenoid flows as a current to the horizontal MOSFET. Therefore, a current which flows to a parasitic transistor is reduced and it is possible to suppress the current which flows to the parasitic transistor provided in the horizontal MOSFET. Since the current which flows to the parasitic transistor is reduced, it is possible to prevent the erroneous operation and breakdown of a semiconductor device forming a synchronous rectification circuit.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A diffusion diode including a p+ diffusion region, a p-type diffusion region, and an n+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p+ layer and an n+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction. The diffusion diode and the polysilicon diode are reverse-connected by electrically connecting the n+ diffusion region to the n+ layer, thereby forming a lateral protection device. The p+ layer and p+ diffusion region are respectively electrically connected to a high voltage first terminal and a low voltage second terminal of the lateral protection device. The polysilicon diode blocks a forward current generated in the diffusion diode when the electric potential of the first terminal becomes lower than the electric potential of the second terminal.

Abstract: A diffusion diode including a p+ diffusion region, a p-type diffusion region, and an n+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p+ layer and an n+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction. The diffusion diode and the polysilicon diode are reverse-connected by electrically connecting the n+ diffusion region to the n+ layer, thereby forming a lateral protection device. The p+ layer and p+ diffusion region are respectively electrically connected to a high voltage first terminal and a low voltage second terminal of the lateral protection device. The polysilicon diode blocks a forward current generated in the diffusion diode when the electric potential of the first terminal becomes lower than the electric potential of the second terminal.

Abstract: One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract: An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.

Abstract: A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate. A high concentration region is open in a normal time, but is short-circuited to a potential higher than that of a GND pad through a second wiring layer in a screening test time. Thus, a semiconductor device and a method for testing the semiconductor device are provided, in which a protection element can be prevented from breaking down and initial failure of a device which is formed on one and the same semiconductor substrate as the protection element can be detected accurately.

Abstract: One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract: A semiconductor device can ensure predetermined current capacity under maintaining breakdown voltage characteristics and can promote size reduction. A first n-type offset-diffusion-region is disposed inside a p-type well region. In the first n-type offset-diffusion-region, a LOCOS film is disposed on the surface layer of a part sandwiched between an n+-type drain region and n+-type source region. In the first n-type offset-diffusion-region, a gate electrode is disposed on the part sandwiched between the LOCOS film and the n+-type source region. In the first n-type offset-diffusion-region, impurity concentration is lower at the part beneath the gate electrode than at the part beneath the LOCOS film. Inside the first n-type offset-diffusion-region, a second n?-type offset-diffusion-region is disposed at apart located toward the n+-type source region through the LOCOS film so as to be separated from the LOCOS film by a distance x.