Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n?semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Abstract: A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area.

Abstract: In certain aspects of the invention, an isolator is configured by a reception circuit, a transmission circuit, and a transformer. In some aspects, the transmission circuit is disposed in an anterior surface of a semiconductor substrate. The transformer is disposed in a posterior surface of the semiconductor substrate and transmits in an electrically isolated state to the reception circuit, a signal input from the transmission circuit. The transformer is configured by a primary coil and a secondary coil. The primary coil can be configured by a metal film embedded in an oxide film inside a coil trench. The secondary coil can be disposed inside an insulating film covering the primary coil so as to oppose the primary coil and is insulated from the primary coil by the insulating film.

Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.

Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.

Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n? semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Abstract: A horizontal MOSFET is arranged in parallel to a horizontal MOSFET and a portion of a return current IL which flows to a linear solenoid flows as a current to the horizontal MOSFET. Therefore, a current which flows to a parasitic transistor is reduced and it is possible to suppress the current which flows to the parasitic transistor provided in the horizontal MOSFET. Since the current which flows to the parasitic transistor is reduced, it is possible to prevent the erroneous operation and breakdown of a semiconductor device forming a synchronous rectification circuit.

Abstract: A semiconductor device can ensure predetermined current capacity under maintaining breakdown voltage characteristics and can promote size reduction. A first n-type offset-diffusion-region is disposed inside a p-type well region. In the first n-type offset-diffusion-region, a LOCOS film is disposed on the surface layer of a part sandwiched between an n+-type drain region and n+-type source region. In the first n-type offset-diffusion-region, a gate electrode is disposed on the part sandwiched between the LOCOS film and the n+-type source region. In the first n-type offset-diffusion-region, impurity concentration is lower at the part beneath the gate electrode than at the part beneath the LOCOS film. Inside the first n-type offset-diffusion-region, a second n?-type offset-diffusion-region is disposed at apart located toward the n+-type source region through the LOCOS film so as to be separated from the LOCOS film by a distance x.

Abstract: By connecting a protection diode (71) wherein p-anode layers (21) and n-cathode layers (22) are alternately formed in a polysilicon layer, and p-n junctions (74) that are in a reverse blocking state when there is a forward bias are alternately short circuited with a metal film (53), to a power semiconductor element (IGBT (72)), it is possible to achieve a balance between a high breakdown capability and a smaller chip area, a rise of breakdown voltage is suppressed even when a clamping voltage is repeatedly applied, and furthermore, it is possible to prevent destruction caused by a negative surge voltage input into a gate terminal (G).

Abstract: Current detection circuit of a semiconductor device provided with a shunt resistor, a voltage division ratio adjustment resistor and a selection circuit which selects a voltage division ratio of the latter and has enhancement type MOSFETs and Zener Zaps as trimming elements. One of the Zener Zaps is trimmed and a divided voltage of the voltage division ratio adjustment resistor connected in parallel with the shunt resistor is outputted. The detected voltage in which variation of the resistance of the shunt resistor has been cancelled is therefore outputted. As the shunt resistor and the voltage division ratio adjustment resistor are laminated together, it is possible to obtain a current detection circuit with a small area, which can detect a current flowing into a shunt resistor with high accuracy.

Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n? semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Abstract: An open load and a supply fault are differentiated between and detected with a simple configuration. A switching element (Q1) connected between the positive electrode of a direct current power supply and an output terminal (9) is caused to carry out a switching operation, thereby driving a load (7) connected to the output terminal (9). A load trouble detection circuit (21) that detects an opening of the load (7) or a supply fault when the voltage of the output terminal (9) is higher than the value of a first threshold voltage, and a supply fault detection circuit (25) that detects a failure of supply to the power supply of the load (7) when the voltage of the output terminal (9) is higher than the value of a second threshold value voltage subtracted from the power supply voltage when the switching element (Q1) is in an off-state, are included.

Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n? semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Abstract: A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area.

Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n?semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.

Abstract: An open load and a supply fault are differentiated between and detected with a simple configuration. A switching element (Q1) connected between the positive electrode of a direct current power supply and an output terminal (9) is caused to carry out a switching operation, thereby driving a load (7) connected to the output terminal (9). A load trouble detection circuit (21) that detects an opening of the load (7) or a supply fault when the voltage of the output terminal (9) is higher than the value of a first threshold voltage, and a supply fault detection circuit (25) that detects a failure of supply to the power supply of the load (7) when the voltage of the output terminal (9) is higher than the value of a second threshold value voltage subtracted from the power supply voltage when the switching element (Q1) is in an off-state, are included.

Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.

Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.

Abstract: In certain aspects of the invention, an isolator is configured by a reception circuit, a transmission circuit, and a transformer. In some aspects, the transmission circuit is disposed in an anterior surface of a semiconductor substrate. The transformer is disposed in a posterior surface of the semiconductor substrate and transmits in an electrically isolated state to the reception circuit, a signal input from the transmission circuit. The transformer is configured by a primary coil and a secondary coil. The primary coil can be configured by a metal film embedded in an oxide film inside a coil trench. The secondary coil can be disposed inside an insulating film covering the primary coil so as to oppose the primary coil and is insulated from the primary coil by the insulating film.