Patents by Inventor Yoshihiko Kamata
Yoshihiko Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220068953Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
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Patent number: 11227869Abstract: Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.Type: GrantFiled: December 4, 2020Date of Patent: January 18, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Publication number: 20220013450Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Micron Technology, Inc.Inventors: Naveen Kaushik, Yoshihiko Kamata, Richard J. Hill, Kyle A. Ritter, Tomoko Ogura Iwasaki, Haitao Liu
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Publication number: 20210383868Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Patent number: 11133066Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: GrantFiled: July 21, 2020Date of Patent: September 28, 2021Assignee: KIOXIA CORPORATIONInventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
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Patent number: 11114166Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.Type: GrantFiled: September 5, 2019Date of Patent: September 7, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Okuyama, Yoshihiko Kamata, Hiromitsu Komai, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Hiroyuki Kaga
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Publication number: 20210233596Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Applicant: Toshiba Memory CorporationInventors: Yoshihiko KAMATA, Naofumi ABIKO
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Patent number: 11011241Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: GrantFiled: December 14, 2018Date of Patent: May 18, 2021Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Naofumi Abiko
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Patent number: 10957403Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.Type: GrantFiled: August 23, 2019Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoko Deguchi, Masahiro Yoshihara, Yoshihiko Kamata, Takuyo Kodama
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Publication number: 20210074361Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Inventors: Mai SHIMIZU, Koji Kato, Yoshihiko KAMATA, Mario Sako
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Patent number: 10872668Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.Type: GrantFiled: February 22, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mai Shimizu, Koji Kato, Yoshihiko Kamata, Mario Sako
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Patent number: 10861536Abstract: A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.Type: GrantFiled: September 4, 2019Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Publication number: 20200350016Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Patent number: 10762963Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.Type: GrantFiled: September 2, 2018Date of Patent: September 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
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Patent number: 10755791Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.Type: GrantFiled: March 4, 2019Date of Patent: August 25, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Patent number: 10720220Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.Type: GrantFiled: April 17, 2019Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Yoko Deguchi, Takuyo Kodama, Tsukasa Kobayashi, Mario Sako, Kosuke Yanagidaira
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Publication number: 20200202956Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.Type: ApplicationFiled: August 23, 2019Publication date: June 25, 2020Inventors: Yoko DEGUCHI, Masahiro YOSHIHARA, Yoshihiko KAMATA, Takuyo KODAMA
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Publication number: 20200202948Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.Type: ApplicationFiled: September 5, 2019Publication date: June 25, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Atsushi OKUYAMA, Yoshihiko KAMATA, Hiromitsu KOMAI, Takuyo KODAMA, Yuki ISHIZAKI, Yoko DEGUCHI, Hiroyuki KAGA
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Publication number: 20200135271Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation being read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.Type: ApplicationFiled: September 4, 2019Publication date: April 30, 2020Applicant: Toshiba Memory CorporationInventors: Yoshihiko KAMATA, Takuyo KODAMA, Yuki ISHIZAKI, Yoko DEGUCHI
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Publication number: 20200098435Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.Type: ApplicationFiled: March 4, 2019Publication date: March 26, 2020Applicant: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi