Patents by Inventor Yoshihiko Kamata
Yoshihiko Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150255162Abstract: According to one embodiment, a semiconductor memory device includes a leak current detection circuit that includes: a detection input end connected to a word line; a first detection end; a coupling circuit connected between the detection input end and the first detection end; a first switching circuit that supplies a voltage to be a reference to the first detection end according to a control signal; and an output circuit that outputs a detection signal corresponding to a change in a voltage of the first detection end caused by the detection input end and the first detection end being coupled by the coupling circuit.Type: ApplicationFiled: September 10, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yuzuru SHIBAZAKI, Dai NAKAMURA, Yoshihiko KAMATA
-
Patent number: 9042183Abstract: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.Type: GrantFiled: September 6, 2013Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiko Kamata, Koji Tabata, Tomoyuki Hamano
-
Publication number: 20150071005Abstract: A NAND type flash memory includes a plurality of memory cells, a bit line electrically connected to a first end of the memory cells, a source line electrically connected to a second end of the memory cells, and a control unit configured to carry out one of first and second sense operations, the first sense operation being carried out when a first read command is received and the second sense operation being carried out when a second read command is received, the first read command being different from the second read command.Type: ApplicationFiled: February 27, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi MAEJIMA, Yoshihiko KAMATA
-
Publication number: 20140286104Abstract: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko KAMATA, Koji TABATA, Tomoyuki HAMANO
-
Publication number: 20140269096Abstract: A first transistor can transfer a first voltage to a bit line. A latch circuit is electrically connected to a gate of the first transistor. A sensing portion is electrically connected to the bit line. A second transistor is connected to the sensing portion and the latch circuit. A third transistor is connected to the sensing portion and the bit line. A fourth transistor is connected to the second transistor and configured to transfer a first value corresponding to a voltage of the sensing node to the latch circuit. A first result is transferred as the first value to the latch circuit through the second and fourth transistor. The first result is obtained by turning on the third transistor for first and second periods. The first transistor transfers one of a ground potential and a second voltage to the bit line, as a voltage corresponding to the first result.Type: ApplicationFiled: September 6, 2013Publication date: September 18, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko Kamata, Koji Tabata
-
Publication number: 20130286738Abstract: According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read.Type: ApplicationFiled: March 15, 2013Publication date: October 31, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yoshihiko KAMATA
-
Publication number: 20130279255Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.Type: ApplicationFiled: March 15, 2013Publication date: October 24, 2013Inventors: Yoshihiko KAMATA, Yuko YOKOTA, Koji TABATA, Tomoyuki HAMANO, Mario SAKO
-
Publication number: 20130279254Abstract: According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.Type: ApplicationFiled: March 15, 2013Publication date: October 24, 2013Inventors: Yoshihiko KAMATA, Koji TABATA, Mitsuhiro KOGA, Tomoyuki HAMANO, Yuko YOKOTA
-
Patent number: 8514636Abstract: According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.Type: GrantFiled: September 18, 2011Date of Patent: August 20, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiko Kamata, Fumitaka Taniwaki, Hirotaka Kariya, Yuki Shimizu, Shirou Fujita
-
Patent number: 8358545Abstract: According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line.Type: GrantFiled: September 18, 2011Date of Patent: January 22, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Mario Sako, Yoshihiko Kamata
-
Patent number: 8238154Abstract: A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.Type: GrantFiled: September 2, 2009Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mario Sako, Jun Fujimoto, Noriyasu Kumazaki, Yasuhiko Honda, Yoshihiko Kamata
-
Publication number: 20120113724Abstract: According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line.Type: ApplicationFiled: September 18, 2011Publication date: May 10, 2012Inventors: Mario SAKO, Yoshihiko Kamata
-
Publication number: 20120069683Abstract: According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.Type: ApplicationFiled: September 18, 2011Publication date: March 22, 2012Inventors: Yoshihiko KAMATA, Fumitaka Taniwaki, Hirotaka Kariya, Yuki Shimizu, Shirou Fujita
-
Patent number: 7813182Abstract: A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.Type: GrantFiled: November 17, 2008Date of Patent: October 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiko Kamata, Takayuki Harima, Yasuhiko Honda
-
Publication number: 20100238736Abstract: 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison.Type: ApplicationFiled: February 25, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko Kamata, Jin Kashiwagi, Hikaru Mochizuki
-
Publication number: 20100214837Abstract: A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.Type: ApplicationFiled: September 2, 2009Publication date: August 26, 2010Inventors: Mario SAKO, Jun Fujimoto, Noriyasu Kumazaki, Yasuhiko Honda, Yoshihiko Kamata
-
Patent number: 7750727Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.Type: GrantFiled: October 29, 2008Date of Patent: July 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Kuwagata, Yasuhiko Honda, Yoshihiko Kamata
-
Patent number: 7751252Abstract: A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.Type: GrantFiled: November 19, 2008Date of Patent: July 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Jin Kashiwagi, Yasuhiko Honda, Yoshihiko Kamata
-
Publication number: 20090135657Abstract: A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.Type: ApplicationFiled: November 17, 2008Publication date: May 28, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yoshihiko KAMATA, Takayuki HARIMA, Yasuhiko HONDA
-
Publication number: 20090129148Abstract: A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.Type: ApplicationFiled: November 19, 2008Publication date: May 21, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jin KASHIWAGI, Yasuhiko HONDA, Yoshihiko KAMATA